[PATCH] x86_64: Remove unused segments

[mirror_ubuntu-artful-kernel.git] / arch / x86_64 / kernel / head.S

diff --git a/arch/x86_64/kernel/head.S b/arch/x86_64/kernel/head.S
index b92e5f45ed46743ab03fbd7e2dbb4c44da5057ab..38fc3d5112e77cfbd66df249227440c6fa66edf1 100644 (file)
--- a/arch/x86_64/kernel/head.S
+++ b/arch/x86_64/kernel/head.S
@@ -12,6 +12,7 @@
 
 #include <linux/linkage.h>
 #include <linux/threads.h>
+#include <linux/init.h>
 #include <asm/desc.h>
 #include <asm/segment.h>
 #include <asm/page.h>
@@ -70,7 +71,7 @@ startup_32:
        movl    %eax, %cr4
 
        /* Setup early boot stage 4 level pagetables */
-       movl    $(init_level4_pgt - __START_KERNEL_map), %eax
+       movl    $(boot_level4_pgt - __START_KERNEL_map), %eax
        movl    %eax, %cr3
 
        /* Setup EFER (Extended Feature Enable Register) */
@@ -113,7 +114,7 @@ startup_64:
        movq    %rax, %cr4
 
        /* Setup early boot stage 4 level pagetables. */
-       movq    $(init_level4_pgt - __START_KERNEL_map), %rax
+       movq    $(boot_level4_pgt - __START_KERNEL_map), %rax
        movq    %rax, %cr3
 
        /* Check if nx is implemented */
@@ -240,20 +241,10 @@ ljumpvector:
 ENTRY(stext)
 ENTRY(_stext)
 
-       /*
-        * This default setting generates an ident mapping at address 0x100000
-        * and a mapping for the kernel that precisely maps virtual address
-        * 0xffffffff80000000 to physical address 0x000000. (always using
-        * 2Mbyte large pages provided by PAE mode)
-        */
 .org 0x1000
 ENTRY(init_level4_pgt)
-       .quad   0x0000000000002007 + __PHYSICAL_START   /* -> level3_ident_pgt */
-       .fill   255,8,0
-       .quad   0x000000000000a007 + __PHYSICAL_START
-       .fill   254,8,0
-       /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
-       .quad   0x0000000000003007 + __PHYSICAL_START   /* -> level3_kernel_pgt */
+       /* This gets initialized in x86_64_start_kernel */
+       .fill   512,8,0
 
 .org 0x2000
 ENTRY(level3_ident_pgt)
@@ -350,6 +341,24 @@ ENTRY(wakeup_level4_pgt)
        .quad   0x0000000000003007 + __PHYSICAL_START   /* -> level3_kernel_pgt */
 #endif
 
+#ifndef CONFIG_HOTPLUG_CPU
+       __INITDATA
+#endif
+       /*
+        * This default setting generates an ident mapping at address 0x100000
+        * and a mapping for the kernel that precisely maps virtual address
+        * 0xffffffff80000000 to physical address 0x000000. (always using
+        * 2Mbyte large pages provided by PAE mode)
+        */
+       .align PAGE_SIZE
+ENTRY(boot_level4_pgt)
+       .quad   0x0000000000002007 + __PHYSICAL_START   /* -> level3_ident_pgt */
+       .fill   255,8,0
+       .quad   0x000000000000a007 + __PHYSICAL_START
+       .fill   254,8,0
+       /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
+       .quad   0x0000000000003007 + __PHYSICAL_START   /* -> level3_kernel_pgt */
+
        .data
 
        .align 16
@@ -370,14 +379,14 @@ gdt:
  * Also sysret mandates a special GDT layout 
  */
                                
-.align L1_CACHE_BYTES
+.align PAGE_SIZE
 
 /* The TLS descriptors are currently at a different place compared to i386.
    Hopefully nobody expects them at a fixed place (Wine?) */
        
 ENTRY(cpu_gdt_table)
        .quad   0x0000000000000000      /* NULL descriptor */
-       .quad   0x008f9a000000ffff      /* __KERNEL_COMPAT32_CS */      
+       .quad   0x0                     /* unused */
        .quad   0x00af9a000000ffff      /* __KERNEL_CS */
        .quad   0x00cf92000000ffff      /* __KERNEL_DS */
        .quad   0x00cffa000000ffff      /* __USER32_CS */
@@ -387,15 +396,15 @@ ENTRY(cpu_gdt_table)
        .quad   0,0                     /* TSS */
        .quad   0,0                     /* LDT */
        .quad   0,0,0                   /* three TLS descriptors */ 
-       .quad   0x00009a000000ffff      /* __KERNEL16_CS - 16bit PM for S3 wakeup. */
-                                       /* base must be patched for real base address. */
+       .quad   0                       /* unused */
 gdt_end:       
        /* asm/segment.h:GDT_ENTRIES must match this */ 
        /* This should be a multiple of the cache line size */
-       /* GDTs of other CPUs: */       
-       .fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)
+       /* GDTs of other CPUs are now dynamically allocated */
+
+       /* zero the remaining page */
+       .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
 
-       .align  L1_CACHE_BYTES
 ENTRY(idt_table)       
        .rept   256
        .quad   0