New upstream version 1.61.0+dfsg1

[rustc.git] / compiler / rustc_target / src / spec / thumbv7em_none_eabihf.rs

diff --git a/compiler/rustc_target/src/spec/thumbv7em_none_eabihf.rs b/compiler/rustc_target/src/spec/thumbv7em_none_eabihf.rs
index 65fc0db65285d8b936ceea752ff0d3e5dd0f50da..39a72564e49a2a504b4d7dc7b4d328f93c8a83d3 100644 (file)
--- a/compiler/rustc_target/src/spec/thumbv7em_none_eabihf.rs
+++ b/compiler/rustc_target/src/spec/thumbv7em_none_eabihf.rs
@@ -12,13 +12,13 @@ use crate::spec::{Target, TargetOptions};
 
 pub fn target() -> Target {
     Target {
-        llvm_target: "thumbv7em-none-eabihf".to_string(),
+        llvm_target: "thumbv7em-none-eabihf".into(),
         pointer_width: 32,
-        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(),
-        arch: "arm".to_string(),
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: "arm".into(),
 
         options: TargetOptions {
-            abi: "eabihf".to_string(),
+            abi: "eabihf".into(),
             // `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
             // Cortex-M7 (vfp5)
             // `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
@@ -28,7 +28,7 @@ pub fn target() -> Target {
             //
             // Reference:
             // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension
-            features: "+vfp4,-d32,-fp64".to_string(),
+            features: "+vfp4,-d32,-fp64".into(),
             max_atomic_width: Some(32),
             ..super::thumb_base::opts()
         },