linux-user: Add emulation for MADV_WIPEONFORK and MADV_KEEPONFORK in madvise()

[mirror_qemu.git] / disas / alpha.c

diff --git a/disas/alpha.c b/disas/alpha.c
index b7b0ae0d929a88d2a4a979d246d71ce142c57238..3db90fa665cdffd730993cb4e3d05be7b6a35ed0 100644 (file)
--- a/disas/alpha.c
+++ b/disas/alpha.c
@@ -20,7 +20,7 @@ along with this file; see the file COPYING.  If not, see
 <http://www.gnu.org/licenses/>. */
 
 #include "qemu/osdep.h"
-#include "disas/bfd.h"
+#include "disas/dis-asm.h"
 
 /* MAX is redefined below, so remove any previous definition. */
 #undef MAX
@@ -672,7 +672,7 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
    OPCODE      is the instruction opcode.
 
    MASK                is the opcode mask; this is used to tell the disassembler
-               which bits in the actual opcode must match OPCODE.
+               which bits in the actual opcode must match OPCODE.
 
    OPERANDS    is the list of operands.
 
@@ -699,10 +699,10 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
    And two annotations:
 
    EV56 BUT    opcodes that are officially introduced as of the ev56,
-               but with defined results on previous implementations.
+               but with defined results on previous implementations.
 
    EV56 UNA    opcodes that were introduced as of the ev56 with
-               presumably undefined results on previous implementations
+               presumably undefined results on previous implementations
                that were not assigned to a particular extension.
 */
 
@@ -832,7 +832,7 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "cmovgt",          OPR(0x11,0x66), BASE, ARG_OPR },
   { "cmovgt",          OPRL(0x11,0x66), BASE, ARG_OPRL },
   { "implver",         OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
-                       0xFFFFFFE0, BASE, { RC } },             /* ev56 but */
+                       0xFFFFFFE0, BASE, { RC } },             /* ev56 but */
 
   { "mskbl",           OPR(0x12,0x02), BASE, ARG_OPR },
   { "mskbl",           OPRL(0x12,0x02), BASE, ARG_OPRL },