*/
#include "qemu/osdep.h"
+#include "qemu/bitops.h"
#include "disas/dis-asm.h"
+#include "target/riscv/cpu_cfg.h"
+#include "disas/riscv.h"
-
-/* types */
-
-typedef uint64_t rv_inst;
-typedef uint16_t rv_opcode;
-
-/* enums */
-
-typedef enum {
- rv32,
- rv64,
- rv128
-} rv_isa;
-
-typedef enum {
- rv_rm_rne = 0,
- rv_rm_rtz = 1,
- rv_rm_rdn = 2,
- rv_rm_rup = 3,
- rv_rm_rmm = 4,
- rv_rm_dyn = 7,
-} rv_rm;
-
-typedef enum {
- rv_fence_i = 8,
- rv_fence_o = 4,
- rv_fence_r = 2,
- rv_fence_w = 1,
-} rv_fence;
-
-typedef enum {
- rv_ireg_zero,
- rv_ireg_ra,
- rv_ireg_sp,
- rv_ireg_gp,
- rv_ireg_tp,
- rv_ireg_t0,
- rv_ireg_t1,
- rv_ireg_t2,
- rv_ireg_s0,
- rv_ireg_s1,
- rv_ireg_a0,
- rv_ireg_a1,
- rv_ireg_a2,
- rv_ireg_a3,
- rv_ireg_a4,
- rv_ireg_a5,
- rv_ireg_a6,
- rv_ireg_a7,
- rv_ireg_s2,
- rv_ireg_s3,
- rv_ireg_s4,
- rv_ireg_s5,
- rv_ireg_s6,
- rv_ireg_s7,
- rv_ireg_s8,
- rv_ireg_s9,
- rv_ireg_s10,
- rv_ireg_s11,
- rv_ireg_t3,
- rv_ireg_t4,
- rv_ireg_t5,
- rv_ireg_t6,
-} rv_ireg;
-
-typedef enum {
- rvc_end,
- rvc_rd_eq_ra,
- rvc_rd_eq_x0,
- rvc_rs1_eq_x0,
- rvc_rs2_eq_x0,
- rvc_rs2_eq_rs1,
- rvc_rs1_eq_ra,
- rvc_imm_eq_zero,
- rvc_imm_eq_n1,
- rvc_imm_eq_p1,
- rvc_csr_eq_0x001,
- rvc_csr_eq_0x002,
- rvc_csr_eq_0x003,
- rvc_csr_eq_0xc00,
- rvc_csr_eq_0xc01,
- rvc_csr_eq_0xc02,
- rvc_csr_eq_0xc80,
- rvc_csr_eq_0xc81,
- rvc_csr_eq_0xc82,
-} rvc_constraint;
+/* Vendor extensions */
+#include "disas/riscv-xthead.h"
+#include "disas/riscv-xventana.h"
typedef enum {
- rv_codec_illegal,
- rv_codec_none,
- rv_codec_u,
- rv_codec_uj,
- rv_codec_i,
- rv_codec_i_sh5,
- rv_codec_i_sh6,
- rv_codec_i_sh7,
- rv_codec_i_csr,
- rv_codec_s,
- rv_codec_sb,
- rv_codec_r,
- rv_codec_r_m,
- rv_codec_r4_m,
- rv_codec_r_a,
- rv_codec_r_l,
- rv_codec_r_f,
- rv_codec_cb,
- rv_codec_cb_imm,
- rv_codec_cb_sh5,
- rv_codec_cb_sh6,
- rv_codec_ci,
- rv_codec_ci_sh5,
- rv_codec_ci_sh6,
- rv_codec_ci_16sp,
- rv_codec_ci_lwsp,
- rv_codec_ci_ldsp,
- rv_codec_ci_lqsp,
- rv_codec_ci_li,
- rv_codec_ci_lui,
- rv_codec_ci_none,
- rv_codec_ciw_4spn,
- rv_codec_cj,
- rv_codec_cj_jal,
- rv_codec_cl_lw,
- rv_codec_cl_ld,
- rv_codec_cl_lq,
- rv_codec_cr,
- rv_codec_cr_mv,
- rv_codec_cr_jalr,
- rv_codec_cr_jr,
- rv_codec_cs,
- rv_codec_cs_sw,
- rv_codec_cs_sd,
- rv_codec_cs_sq,
- rv_codec_css_swsp,
- rv_codec_css_sdsp,
- rv_codec_css_sqsp,
- rv_codec_k_bs,
- rv_codec_k_rnum,
-} rv_codec;
-
-typedef enum {
- rv_op_illegal = 0,
+ /* 0 is reserved for rv_op_illegal. */
rv_op_lui = 1,
rv_op_auipc = 2,
rv_op_jal = 3,
rv_op_zip = 396,
rv_op_xperm4 = 397,
rv_op_xperm8 = 398,
+ rv_op_vle8_v = 399,
+ rv_op_vle16_v = 400,
+ rv_op_vle32_v = 401,
+ rv_op_vle64_v = 402,
+ rv_op_vse8_v = 403,
+ rv_op_vse16_v = 404,
+ rv_op_vse32_v = 405,
+ rv_op_vse64_v = 406,
+ rv_op_vlm_v = 407,
+ rv_op_vsm_v = 408,
+ rv_op_vlse8_v = 409,
+ rv_op_vlse16_v = 410,
+ rv_op_vlse32_v = 411,
+ rv_op_vlse64_v = 412,
+ rv_op_vsse8_v = 413,
+ rv_op_vsse16_v = 414,
+ rv_op_vsse32_v = 415,
+ rv_op_vsse64_v = 416,
+ rv_op_vluxei8_v = 417,
+ rv_op_vluxei16_v = 418,
+ rv_op_vluxei32_v = 419,
+ rv_op_vluxei64_v = 420,
+ rv_op_vloxei8_v = 421,
+ rv_op_vloxei16_v = 422,
+ rv_op_vloxei32_v = 423,
+ rv_op_vloxei64_v = 424,
+ rv_op_vsuxei8_v = 425,
+ rv_op_vsuxei16_v = 426,
+ rv_op_vsuxei32_v = 427,
+ rv_op_vsuxei64_v = 428,
+ rv_op_vsoxei8_v = 429,
+ rv_op_vsoxei16_v = 430,
+ rv_op_vsoxei32_v = 431,
+ rv_op_vsoxei64_v = 432,
+ rv_op_vle8ff_v = 433,
+ rv_op_vle16ff_v = 434,
+ rv_op_vle32ff_v = 435,
+ rv_op_vle64ff_v = 436,
+ rv_op_vl1re8_v = 437,
+ rv_op_vl1re16_v = 438,
+ rv_op_vl1re32_v = 439,
+ rv_op_vl1re64_v = 440,
+ rv_op_vl2re8_v = 441,
+ rv_op_vl2re16_v = 442,
+ rv_op_vl2re32_v = 443,
+ rv_op_vl2re64_v = 444,
+ rv_op_vl4re8_v = 445,
+ rv_op_vl4re16_v = 446,
+ rv_op_vl4re32_v = 447,
+ rv_op_vl4re64_v = 448,
+ rv_op_vl8re8_v = 449,
+ rv_op_vl8re16_v = 450,
+ rv_op_vl8re32_v = 451,
+ rv_op_vl8re64_v = 452,
+ rv_op_vs1r_v = 453,
+ rv_op_vs2r_v = 454,
+ rv_op_vs4r_v = 455,
+ rv_op_vs8r_v = 456,
+ rv_op_vadd_vv = 457,
+ rv_op_vadd_vx = 458,
+ rv_op_vadd_vi = 459,
+ rv_op_vsub_vv = 460,
+ rv_op_vsub_vx = 461,
+ rv_op_vrsub_vx = 462,
+ rv_op_vrsub_vi = 463,
+ rv_op_vwaddu_vv = 464,
+ rv_op_vwaddu_vx = 465,
+ rv_op_vwadd_vv = 466,
+ rv_op_vwadd_vx = 467,
+ rv_op_vwsubu_vv = 468,
+ rv_op_vwsubu_vx = 469,
+ rv_op_vwsub_vv = 470,
+ rv_op_vwsub_vx = 471,
+ rv_op_vwaddu_wv = 472,
+ rv_op_vwaddu_wx = 473,
+ rv_op_vwadd_wv = 474,
+ rv_op_vwadd_wx = 475,
+ rv_op_vwsubu_wv = 476,
+ rv_op_vwsubu_wx = 477,
+ rv_op_vwsub_wv = 478,
+ rv_op_vwsub_wx = 479,
+ rv_op_vadc_vvm = 480,
+ rv_op_vadc_vxm = 481,
+ rv_op_vadc_vim = 482,
+ rv_op_vmadc_vvm = 483,
+ rv_op_vmadc_vxm = 484,
+ rv_op_vmadc_vim = 485,
+ rv_op_vsbc_vvm = 486,
+ rv_op_vsbc_vxm = 487,
+ rv_op_vmsbc_vvm = 488,
+ rv_op_vmsbc_vxm = 489,
+ rv_op_vand_vv = 490,
+ rv_op_vand_vx = 491,
+ rv_op_vand_vi = 492,
+ rv_op_vor_vv = 493,
+ rv_op_vor_vx = 494,
+ rv_op_vor_vi = 495,
+ rv_op_vxor_vv = 496,
+ rv_op_vxor_vx = 497,
+ rv_op_vxor_vi = 498,
+ rv_op_vsll_vv = 499,
+ rv_op_vsll_vx = 500,
+ rv_op_vsll_vi = 501,
+ rv_op_vsrl_vv = 502,
+ rv_op_vsrl_vx = 503,
+ rv_op_vsrl_vi = 504,
+ rv_op_vsra_vv = 505,
+ rv_op_vsra_vx = 506,
+ rv_op_vsra_vi = 507,
+ rv_op_vnsrl_wv = 508,
+ rv_op_vnsrl_wx = 509,
+ rv_op_vnsrl_wi = 510,
+ rv_op_vnsra_wv = 511,
+ rv_op_vnsra_wx = 512,
+ rv_op_vnsra_wi = 513,
+ rv_op_vmseq_vv = 514,
+ rv_op_vmseq_vx = 515,
+ rv_op_vmseq_vi = 516,
+ rv_op_vmsne_vv = 517,
+ rv_op_vmsne_vx = 518,
+ rv_op_vmsne_vi = 519,
+ rv_op_vmsltu_vv = 520,
+ rv_op_vmsltu_vx = 521,
+ rv_op_vmslt_vv = 522,
+ rv_op_vmslt_vx = 523,
+ rv_op_vmsleu_vv = 524,
+ rv_op_vmsleu_vx = 525,
+ rv_op_vmsleu_vi = 526,
+ rv_op_vmsle_vv = 527,
+ rv_op_vmsle_vx = 528,
+ rv_op_vmsle_vi = 529,
+ rv_op_vmsgtu_vx = 530,
+ rv_op_vmsgtu_vi = 531,
+ rv_op_vmsgt_vx = 532,
+ rv_op_vmsgt_vi = 533,
+ rv_op_vminu_vv = 534,
+ rv_op_vminu_vx = 535,
+ rv_op_vmin_vv = 536,
+ rv_op_vmin_vx = 537,
+ rv_op_vmaxu_vv = 538,
+ rv_op_vmaxu_vx = 539,
+ rv_op_vmax_vv = 540,
+ rv_op_vmax_vx = 541,
+ rv_op_vmul_vv = 542,
+ rv_op_vmul_vx = 543,
+ rv_op_vmulh_vv = 544,
+ rv_op_vmulh_vx = 545,
+ rv_op_vmulhu_vv = 546,
+ rv_op_vmulhu_vx = 547,
+ rv_op_vmulhsu_vv = 548,
+ rv_op_vmulhsu_vx = 549,
+ rv_op_vdivu_vv = 550,
+ rv_op_vdivu_vx = 551,
+ rv_op_vdiv_vv = 552,
+ rv_op_vdiv_vx = 553,
+ rv_op_vremu_vv = 554,
+ rv_op_vremu_vx = 555,
+ rv_op_vrem_vv = 556,
+ rv_op_vrem_vx = 557,
+ rv_op_vwmulu_vv = 558,
+ rv_op_vwmulu_vx = 559,
+ rv_op_vwmulsu_vv = 560,
+ rv_op_vwmulsu_vx = 561,
+ rv_op_vwmul_vv = 562,
+ rv_op_vwmul_vx = 563,
+ rv_op_vmacc_vv = 564,
+ rv_op_vmacc_vx = 565,
+ rv_op_vnmsac_vv = 566,
+ rv_op_vnmsac_vx = 567,
+ rv_op_vmadd_vv = 568,
+ rv_op_vmadd_vx = 569,
+ rv_op_vnmsub_vv = 570,
+ rv_op_vnmsub_vx = 571,
+ rv_op_vwmaccu_vv = 572,
+ rv_op_vwmaccu_vx = 573,
+ rv_op_vwmacc_vv = 574,
+ rv_op_vwmacc_vx = 575,
+ rv_op_vwmaccsu_vv = 576,
+ rv_op_vwmaccsu_vx = 577,
+ rv_op_vwmaccus_vx = 578,
+ rv_op_vmv_v_v = 579,
+ rv_op_vmv_v_x = 580,
+ rv_op_vmv_v_i = 581,
+ rv_op_vmerge_vvm = 582,
+ rv_op_vmerge_vxm = 583,
+ rv_op_vmerge_vim = 584,
+ rv_op_vsaddu_vv = 585,
+ rv_op_vsaddu_vx = 586,
+ rv_op_vsaddu_vi = 587,
+ rv_op_vsadd_vv = 588,
+ rv_op_vsadd_vx = 589,
+ rv_op_vsadd_vi = 590,
+ rv_op_vssubu_vv = 591,
+ rv_op_vssubu_vx = 592,
+ rv_op_vssub_vv = 593,
+ rv_op_vssub_vx = 594,
+ rv_op_vaadd_vv = 595,
+ rv_op_vaadd_vx = 596,
+ rv_op_vaaddu_vv = 597,
+ rv_op_vaaddu_vx = 598,
+ rv_op_vasub_vv = 599,
+ rv_op_vasub_vx = 600,
+ rv_op_vasubu_vv = 601,
+ rv_op_vasubu_vx = 602,
+ rv_op_vsmul_vv = 603,
+ rv_op_vsmul_vx = 604,
+ rv_op_vssrl_vv = 605,
+ rv_op_vssrl_vx = 606,
+ rv_op_vssrl_vi = 607,
+ rv_op_vssra_vv = 608,
+ rv_op_vssra_vx = 609,
+ rv_op_vssra_vi = 610,
+ rv_op_vnclipu_wv = 611,
+ rv_op_vnclipu_wx = 612,
+ rv_op_vnclipu_wi = 613,
+ rv_op_vnclip_wv = 614,
+ rv_op_vnclip_wx = 615,
+ rv_op_vnclip_wi = 616,
+ rv_op_vfadd_vv = 617,
+ rv_op_vfadd_vf = 618,
+ rv_op_vfsub_vv = 619,
+ rv_op_vfsub_vf = 620,
+ rv_op_vfrsub_vf = 621,
+ rv_op_vfwadd_vv = 622,
+ rv_op_vfwadd_vf = 623,
+ rv_op_vfwadd_wv = 624,
+ rv_op_vfwadd_wf = 625,
+ rv_op_vfwsub_vv = 626,
+ rv_op_vfwsub_vf = 627,
+ rv_op_vfwsub_wv = 628,
+ rv_op_vfwsub_wf = 629,
+ rv_op_vfmul_vv = 630,
+ rv_op_vfmul_vf = 631,
+ rv_op_vfdiv_vv = 632,
+ rv_op_vfdiv_vf = 633,
+ rv_op_vfrdiv_vf = 634,
+ rv_op_vfwmul_vv = 635,
+ rv_op_vfwmul_vf = 636,
+ rv_op_vfmacc_vv = 637,
+ rv_op_vfmacc_vf = 638,
+ rv_op_vfnmacc_vv = 639,
+ rv_op_vfnmacc_vf = 640,
+ rv_op_vfmsac_vv = 641,
+ rv_op_vfmsac_vf = 642,
+ rv_op_vfnmsac_vv = 643,
+ rv_op_vfnmsac_vf = 644,
+ rv_op_vfmadd_vv = 645,
+ rv_op_vfmadd_vf = 646,
+ rv_op_vfnmadd_vv = 647,
+ rv_op_vfnmadd_vf = 648,
+ rv_op_vfmsub_vv = 649,
+ rv_op_vfmsub_vf = 650,
+ rv_op_vfnmsub_vv = 651,
+ rv_op_vfnmsub_vf = 652,
+ rv_op_vfwmacc_vv = 653,
+ rv_op_vfwmacc_vf = 654,
+ rv_op_vfwnmacc_vv = 655,
+ rv_op_vfwnmacc_vf = 656,
+ rv_op_vfwmsac_vv = 657,
+ rv_op_vfwmsac_vf = 658,
+ rv_op_vfwnmsac_vv = 659,
+ rv_op_vfwnmsac_vf = 660,
+ rv_op_vfsqrt_v = 661,
+ rv_op_vfrsqrt7_v = 662,
+ rv_op_vfrec7_v = 663,
+ rv_op_vfmin_vv = 664,
+ rv_op_vfmin_vf = 665,
+ rv_op_vfmax_vv = 666,
+ rv_op_vfmax_vf = 667,
+ rv_op_vfsgnj_vv = 668,
+ rv_op_vfsgnj_vf = 669,
+ rv_op_vfsgnjn_vv = 670,
+ rv_op_vfsgnjn_vf = 671,
+ rv_op_vfsgnjx_vv = 672,
+ rv_op_vfsgnjx_vf = 673,
+ rv_op_vfslide1up_vf = 674,
+ rv_op_vfslide1down_vf = 675,
+ rv_op_vmfeq_vv = 676,
+ rv_op_vmfeq_vf = 677,
+ rv_op_vmfne_vv = 678,
+ rv_op_vmfne_vf = 679,
+ rv_op_vmflt_vv = 680,
+ rv_op_vmflt_vf = 681,
+ rv_op_vmfle_vv = 682,
+ rv_op_vmfle_vf = 683,
+ rv_op_vmfgt_vf = 684,
+ rv_op_vmfge_vf = 685,
+ rv_op_vfclass_v = 686,
+ rv_op_vfmerge_vfm = 687,
+ rv_op_vfmv_v_f = 688,
+ rv_op_vfcvt_xu_f_v = 689,
+ rv_op_vfcvt_x_f_v = 690,
+ rv_op_vfcvt_f_xu_v = 691,
+ rv_op_vfcvt_f_x_v = 692,
+ rv_op_vfcvt_rtz_xu_f_v = 693,
+ rv_op_vfcvt_rtz_x_f_v = 694,
+ rv_op_vfwcvt_xu_f_v = 695,
+ rv_op_vfwcvt_x_f_v = 696,
+ rv_op_vfwcvt_f_xu_v = 697,
+ rv_op_vfwcvt_f_x_v = 698,
+ rv_op_vfwcvt_f_f_v = 699,
+ rv_op_vfwcvt_rtz_xu_f_v = 700,
+ rv_op_vfwcvt_rtz_x_f_v = 701,
+ rv_op_vfncvt_xu_f_w = 702,
+ rv_op_vfncvt_x_f_w = 703,
+ rv_op_vfncvt_f_xu_w = 704,
+ rv_op_vfncvt_f_x_w = 705,
+ rv_op_vfncvt_f_f_w = 706,
+ rv_op_vfncvt_rod_f_f_w = 707,
+ rv_op_vfncvt_rtz_xu_f_w = 708,
+ rv_op_vfncvt_rtz_x_f_w = 709,
+ rv_op_vredsum_vs = 710,
+ rv_op_vredand_vs = 711,
+ rv_op_vredor_vs = 712,
+ rv_op_vredxor_vs = 713,
+ rv_op_vredminu_vs = 714,
+ rv_op_vredmin_vs = 715,
+ rv_op_vredmaxu_vs = 716,
+ rv_op_vredmax_vs = 717,
+ rv_op_vwredsumu_vs = 718,
+ rv_op_vwredsum_vs = 719,
+ rv_op_vfredusum_vs = 720,
+ rv_op_vfredosum_vs = 721,
+ rv_op_vfredmin_vs = 722,
+ rv_op_vfredmax_vs = 723,
+ rv_op_vfwredusum_vs = 724,
+ rv_op_vfwredosum_vs = 725,
+ rv_op_vmand_mm = 726,
+ rv_op_vmnand_mm = 727,
+ rv_op_vmandn_mm = 728,
+ rv_op_vmxor_mm = 729,
+ rv_op_vmor_mm = 730,
+ rv_op_vmnor_mm = 731,
+ rv_op_vmorn_mm = 732,
+ rv_op_vmxnor_mm = 733,
+ rv_op_vcpop_m = 734,
+ rv_op_vfirst_m = 735,
+ rv_op_vmsbf_m = 736,
+ rv_op_vmsif_m = 737,
+ rv_op_vmsof_m = 738,
+ rv_op_viota_m = 739,
+ rv_op_vid_v = 740,
+ rv_op_vmv_x_s = 741,
+ rv_op_vmv_s_x = 742,
+ rv_op_vfmv_f_s = 743,
+ rv_op_vfmv_s_f = 744,
+ rv_op_vslideup_vx = 745,
+ rv_op_vslideup_vi = 746,
+ rv_op_vslide1up_vx = 747,
+ rv_op_vslidedown_vx = 748,
+ rv_op_vslidedown_vi = 749,
+ rv_op_vslide1down_vx = 750,
+ rv_op_vrgather_vv = 751,
+ rv_op_vrgatherei16_vv = 752,
+ rv_op_vrgather_vx = 753,
+ rv_op_vrgather_vi = 754,
+ rv_op_vcompress_vm = 755,
+ rv_op_vmv1r_v = 756,
+ rv_op_vmv2r_v = 757,
+ rv_op_vmv4r_v = 758,
+ rv_op_vmv8r_v = 759,
+ rv_op_vzext_vf2 = 760,
+ rv_op_vzext_vf4 = 761,
+ rv_op_vzext_vf8 = 762,
+ rv_op_vsext_vf2 = 763,
+ rv_op_vsext_vf4 = 764,
+ rv_op_vsext_vf8 = 765,
+ rv_op_vsetvli = 766,
+ rv_op_vsetivli = 767,
+ rv_op_vsetvl = 768,
+ rv_op_c_zext_b = 769,
+ rv_op_c_sext_b = 770,
+ rv_op_c_zext_h = 771,
+ rv_op_c_sext_h = 772,
+ rv_op_c_zext_w = 773,
+ rv_op_c_not = 774,
+ rv_op_c_mul = 775,
+ rv_op_c_lbu = 776,
+ rv_op_c_lhu = 777,
+ rv_op_c_lh = 778,
+ rv_op_c_sb = 779,
+ rv_op_c_sh = 780,
+ rv_op_cm_push = 781,
+ rv_op_cm_pop = 782,
+ rv_op_cm_popret = 783,
+ rv_op_cm_popretz = 784,
+ rv_op_cm_mva01s = 785,
+ rv_op_cm_mvsa01 = 786,
+ rv_op_cm_jt = 787,
+ rv_op_cm_jalt = 788,
+ rv_op_czero_eqz = 789,
+ rv_op_czero_nez = 790,
+ rv_op_fcvt_bf16_s = 791,
+ rv_op_fcvt_s_bf16 = 792,
+ rv_op_vfncvtbf16_f_f_w = 793,
+ rv_op_vfwcvtbf16_f_f_v = 794,
+ rv_op_vfwmaccbf16_vv = 795,
+ rv_op_vfwmaccbf16_vf = 796,
+ rv_op_flh = 797,
+ rv_op_fsh = 798,
+ rv_op_fmv_h_x = 799,
+ rv_op_fmv_x_h = 800,
+ rv_op_fli_s = 801,
+ rv_op_fli_d = 802,
+ rv_op_fli_q = 803,
+ rv_op_fli_h = 804,
+ rv_op_fminm_s = 805,
+ rv_op_fmaxm_s = 806,
+ rv_op_fminm_d = 807,
+ rv_op_fmaxm_d = 808,
+ rv_op_fminm_q = 809,
+ rv_op_fmaxm_q = 810,
+ rv_op_fminm_h = 811,
+ rv_op_fmaxm_h = 812,
+ rv_op_fround_s = 813,
+ rv_op_froundnx_s = 814,
+ rv_op_fround_d = 815,
+ rv_op_froundnx_d = 816,
+ rv_op_fround_q = 817,
+ rv_op_froundnx_q = 818,
+ rv_op_fround_h = 819,
+ rv_op_froundnx_h = 820,
+ rv_op_fcvtmod_w_d = 821,
+ rv_op_fmvh_x_d = 822,
+ rv_op_fmvp_d_x = 823,
+ rv_op_fmvh_x_q = 824,
+ rv_op_fmvp_q_x = 825,
+ rv_op_fleq_s = 826,
+ rv_op_fltq_s = 827,
+ rv_op_fleq_d = 828,
+ rv_op_fltq_d = 829,
+ rv_op_fleq_q = 830,
+ rv_op_fltq_q = 831,
+ rv_op_fleq_h = 832,
+ rv_op_fltq_h = 833,
+ rv_op_vaesdf_vv = 834,
+ rv_op_vaesdf_vs = 835,
+ rv_op_vaesdm_vv = 836,
+ rv_op_vaesdm_vs = 837,
+ rv_op_vaesef_vv = 838,
+ rv_op_vaesef_vs = 839,
+ rv_op_vaesem_vv = 840,
+ rv_op_vaesem_vs = 841,
+ rv_op_vaeskf1_vi = 842,
+ rv_op_vaeskf2_vi = 843,
+ rv_op_vaesz_vs = 844,
+ rv_op_vandn_vv = 845,
+ rv_op_vandn_vx = 846,
+ rv_op_vbrev_v = 847,
+ rv_op_vbrev8_v = 848,
+ rv_op_vclmul_vv = 849,
+ rv_op_vclmul_vx = 850,
+ rv_op_vclmulh_vv = 851,
+ rv_op_vclmulh_vx = 852,
+ rv_op_vclz_v = 853,
+ rv_op_vcpop_v = 854,
+ rv_op_vctz_v = 855,
+ rv_op_vghsh_vv = 856,
+ rv_op_vgmul_vv = 857,
+ rv_op_vrev8_v = 858,
+ rv_op_vrol_vv = 859,
+ rv_op_vrol_vx = 860,
+ rv_op_vror_vv = 861,
+ rv_op_vror_vx = 862,
+ rv_op_vror_vi = 863,
+ rv_op_vsha2ch_vv = 864,
+ rv_op_vsha2cl_vv = 865,
+ rv_op_vsha2ms_vv = 866,
+ rv_op_vsm3c_vi = 867,
+ rv_op_vsm3me_vv = 868,
+ rv_op_vsm4k_vi = 869,
+ rv_op_vsm4r_vv = 870,
+ rv_op_vsm4r_vs = 871,
+ rv_op_vwsll_vv = 872,
+ rv_op_vwsll_vx = 873,
+ rv_op_vwsll_vi = 874,
} rv_op;
-/* structures */
-
-typedef struct {
- uint64_t pc;
- uint64_t inst;
- int32_t imm;
- uint16_t op;
- uint8_t codec;
- uint8_t rd;
- uint8_t rs1;
- uint8_t rs2;
- uint8_t rs3;
- uint8_t rm;
- uint8_t pred;
- uint8_t succ;
- uint8_t aq;
- uint8_t rl;
- uint8_t bs;
- uint8_t rnum;
-} rv_decode;
-
-typedef struct {
- const int op;
- const rvc_constraint *constraints;
-} rv_comp_data;
-
-enum {
- rvcd_imm_nz = 0x1
-};
-
-typedef struct {
- const char * const name;
- const rv_codec codec;
- const char * const format;
- const rv_comp_data *pseudo;
- const short decomp_rv32;
- const short decomp_rv64;
- const short decomp_rv128;
- const short decomp_data;
-} rv_opcode_data;
-
/* register names */
static const char rv_ireg_name_sym[32][5] = {
"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
};
-/* instruction formats */
-
-#define rv_fmt_none "O\t"
-#define rv_fmt_rs1 "O\t1"
-#define rv_fmt_offset "O\to"
-#define rv_fmt_pred_succ "O\tp,s"
-#define rv_fmt_rs1_rs2 "O\t1,2"
-#define rv_fmt_rd_imm "O\t0,i"
-#define rv_fmt_rd_offset "O\t0,o"
-#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
-#define rv_fmt_frd_rs1 "O\t3,1"
-#define rv_fmt_rd_frs1 "O\t0,4"
-#define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
-#define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
-#define rv_fmt_rm_frd_frs1 "O\tr,3,4"
-#define rv_fmt_rm_frd_rs1 "O\tr,3,1"
-#define rv_fmt_rm_rd_frs1 "O\tr,0,4"
-#define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5"
-#define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6"
-#define rv_fmt_rd_rs1_imm "O\t0,1,i"
-#define rv_fmt_rd_rs1_offset "O\t0,1,i"
-#define rv_fmt_rd_offset_rs1 "O\t0,i(1)"
-#define rv_fmt_frd_offset_rs1 "O\t3,i(1)"
-#define rv_fmt_rd_csr_rs1 "O\t0,c,1"
-#define rv_fmt_rd_csr_zimm "O\t0,c,7"
-#define rv_fmt_rs2_offset_rs1 "O\t2,i(1)"
-#define rv_fmt_frs2_offset_rs1 "O\t5,i(1)"
-#define rv_fmt_rs1_rs2_offset "O\t1,2,o"
-#define rv_fmt_rs2_rs1_offset "O\t2,1,o"
-#define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)"
-#define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)"
-#define rv_fmt_rd "O\t0"
-#define rv_fmt_rd_zimm "O\t0,7"
-#define rv_fmt_rd_rs1 "O\t0,1"
-#define rv_fmt_rd_rs2 "O\t0,2"
-#define rv_fmt_rs1_offset "O\t1,o"
-#define rv_fmt_rs2_offset "O\t2,o"
-#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
-#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
+static const char rv_vreg_name_sym[32][4] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+};
+
+/* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants).
+ * The constants use the hex floating-point literal representation
+ * that is printed when using the printf %a format specifier,
+ * which matches the output that is generated by the disassembler.
+ */
+static const char rv_fli_name_const[32][9] =
+{
+ "0x1p+0", "min", "0x1p-16", "0x1p-15",
+ "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3",
+ "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2",
+ "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1",
+ "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0",
+ "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2",
+ "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8",
+ "0x1p+15", "0x1p+16", "inf", "nan"
+};
/* pseudo-instruction constraints */
static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
+static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
+ rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_bgt[] = { rvc_end };
static const rvc_constraint rvcc_bgtu[] = { rvc_end };
static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
-static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
-static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
-static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
-static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
-static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
+static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
+ rvc_end };
+static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
+ rvc_end };
+static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
+ rvc_end };
+static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc02, rvc_end };
+static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc80, rvc_end };
+static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
+ rvc_end };
static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc82, rvc_end };
-static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
-static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
-static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
+static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
+ rvc_end };
+static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
+ rvc_end };
+static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
+ rvc_end };
static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
/* instruction metadata */
-const rv_opcode_data opcode_data[] = {
+const rv_opcode_data rvi_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
- { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
- { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
+ { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
+ { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
{ "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
{ "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
{ "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
+ { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, 0 },
+ { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
+ rv_op_lw },
{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
+ { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, 0 },
+ { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
+ rv_op_sw },
{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
rv_op_addi, rvcd_imm_nz },
{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
- { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
+ { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
rv_op_lui, rvcd_imm_nz },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
rv_op_srli, rv_op_srli, rvcd_imm_nz },
rv_op_srai, rv_op_srai, rvcd_imm_nz },
{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
+ { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
+ rv_op_sub },
+ { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
+ rv_op_xor },
+ { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
+ rv_op_or },
+ { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
+ rv_op_and },
+ { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
+ rv_op_subw },
+ { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
+ rv_op_addw },
+ { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
+ rv_op_jal },
+ { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
+ rv_op_beq },
+ { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
+ rv_op_bne },
{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
rv_op_slli, rv_op_slli, rvcd_imm_nz },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
+ { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, rv_op_fld },
+ { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
+ rv_op_lw, rv_op_lw },
+ { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
+ 0 },
+ { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
+ { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
+ rv_op_ebreak, rv_op_ebreak },
+ { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
+ rv_op_add },
+ { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, rv_op_fsd },
+ { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
+ rv_op_sw, rv_op_sw },
+ { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
+ 0 },
+ { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
+ { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
+ rv_op_addiw },
+ { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
{ "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
{ "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
+ { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
+ rv_op_sq },
{ "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
{ "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
{ "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
{ "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
{ "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
{ "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
{ "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
+ { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
+ { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
+ { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
+ { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
+ { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
+ { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
+ { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
+ { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
+ { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
+ { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
+ { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
+ { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
+ { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
+ { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
+ { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
+ { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
+ { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
+ { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
+ { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
+ { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
+ { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
+ { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
+ { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
+ { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
+ { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
+ { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
+ { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
+ { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
+ { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
+ { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
+ { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
+ { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
+ { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
+ { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
+ { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
+ { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
};
/* CSR names */
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
+ case 0x0008: return "vstart";
+ case 0x0009: return "vxsat";
+ case 0x000a: return "vxrm";
+ case 0x000f: return "vcsr";
case 0x0015: return "seed";
+ case 0x0017: return "jvt";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
case 0x03ba: return "pmpaddr10";
case 0x03bb: return "pmpaddr11";
case 0x03bc: return "pmpaddr12";
- case 0x03bd: return "pmpaddr14";
- case 0x03be: return "pmpaddr13";
+ case 0x03bd: return "pmpaddr13";
+ case 0x03be: return "pmpaddr14";
case 0x03bf: return "pmpaddr15";
case 0x0780: return "mtohost";
case 0x0781: return "mfromhost";
case 0x0c00: return "cycle";
case 0x0c01: return "time";
case 0x0c02: return "instret";
+ case 0x0c20: return "vl";
+ case 0x0c21: return "vtype";
+ case 0x0c22: return "vlenb";
case 0x0c80: return "cycleh";
case 0x0c81: return "timeh";
case 0x0c82: return "instreth";
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
- switch (((inst >> 0) & 0b11)) {
+ switch ((inst >> 0) & 0b11) {
case 0:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0: op = rv_op_c_addi4spn; break;
case 1:
if (isa == rv128) {
op = rv_op_c_ld;
}
break;
+ case 4:
+ switch ((inst >> 10) & 0b111) {
+ case 0: op = rv_op_c_lbu; break;
+ case 1:
+ if (((inst >> 6) & 1) == 0) {
+ op = rv_op_c_lhu;
+ } else {
+ op = rv_op_c_lh;
+ }
+ break;
+ case 2: op = rv_op_c_sb; break;
+ case 3:
+ if (((inst >> 6) & 1) == 0) {
+ op = rv_op_c_sh;
+ }
+ break;
+ }
+ break;
case 5:
if (isa == rv128) {
op = rv_op_c_sq;
}
break;
case 1:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0:
- switch (((inst >> 2) & 0b11111111111)) {
+ switch ((inst >> 2) & 0b11111111111) {
case 0: op = rv_op_c_nop; break;
default: op = rv_op_c_addi; break;
}
break;
case 2: op = rv_op_c_li; break;
case 3:
- switch (((inst >> 7) & 0b11111)) {
+ switch ((inst >> 7) & 0b11111) {
case 2: op = rv_op_c_addi16sp; break;
default: op = rv_op_c_lui; break;
}
break;
case 4:
- switch (((inst >> 10) & 0b11)) {
+ switch ((inst >> 10) & 0b11) {
case 0:
op = rv_op_c_srli;
break;
case 3: op = rv_op_c_and; break;
case 4: op = rv_op_c_subw; break;
case 5: op = rv_op_c_addw; break;
+ case 6: op = rv_op_c_mul; break;
+ case 7:
+ switch ((inst >> 2) & 0b111) {
+ case 0: op = rv_op_c_zext_b; break;
+ case 1: op = rv_op_c_sext_b; break;
+ case 2: op = rv_op_c_zext_h; break;
+ case 3: op = rv_op_c_sext_h; break;
+ case 4: op = rv_op_c_zext_w; break;
+ case 5: op = rv_op_c_not; break;
+ }
+ break;
}
break;
}
}
break;
case 2:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0:
op = rv_op_c_slli;
break;
}
break;
case 4:
- switch (((inst >> 12) & 0b1)) {
+ switch ((inst >> 12) & 0b1) {
case 0:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0: op = rv_op_c_jr; break;
default: op = rv_op_c_mv; break;
}
break;
case 1:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0:
- switch (((inst >> 7) & 0b11111)) {
+ switch ((inst >> 7) & 0b11111) {
case 0: op = rv_op_c_ebreak; break;
default: op = rv_op_c_jalr; break;
}
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
+ switch ((inst >> 8) & 0b01111) {
+ case 8:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_push;
+ }
+ break;
+ case 10:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_pop;
+ }
+ break;
+ case 12:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_popretz;
+ }
+ break;
+ case 14:
+ if (((inst >> 4) & 0b01111) >= 4) {
+ op = rv_op_cm_popret;
+ }
+ break;
+ }
+ } else {
+ switch ((inst >> 10) & 0b011) {
+ case 0:
+ if (!dec->cfg->ext_zcmt) {
+ break;
+ }
+ if (((inst >> 2) & 0xFF) >= 32) {
+ op = rv_op_cm_jalt;
+ } else {
+ op = rv_op_cm_jt;
+ }
+ break;
+ case 3:
+ if (!dec->cfg->ext_zcmp) {
+ break;
+ }
+ switch ((inst >> 5) & 0b011) {
+ case 1: op = rv_op_cm_mvsa01; break;
+ case 3: op = rv_op_cm_mva01s; break;
+ }
+ break;
+ }
+ }
}
break;
case 6: op = rv_op_c_swsp; break;
}
break;
case 3:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_lb; break;
case 1: op = rv_op_lh; break;
case 2: op = rv_op_lw; break;
}
break;
case 1:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b111111111111) {
+ case 40: op = rv_op_vl1re8_v; break;
+ case 552: op = rv_op_vl2re8_v; break;
+ case 1576: op = rv_op_vl4re8_v; break;
+ case 3624: op = rv_op_vl8re8_v; break;
+ }
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vle8_v; break;
+ case 11: op = rv_op_vlm_v; break;
+ case 16: op = rv_op_vle8ff_v; break;
+ }
+ break;
+ case 1: op = rv_op_vluxei8_v; break;
+ case 2: op = rv_op_vlse8_v; break;
+ case 3: op = rv_op_vloxei8_v; break;
+ }
+ break;
+ case 1: op = rv_op_flh; break;
case 2: op = rv_op_flw; break;
case 3: op = rv_op_fld; break;
case 4: op = rv_op_flq; break;
+ case 5:
+ switch ((inst >> 20) & 0b111111111111) {
+ case 40: op = rv_op_vl1re16_v; break;
+ case 552: op = rv_op_vl2re16_v; break;
+ case 1576: op = rv_op_vl4re16_v; break;
+ case 3624: op = rv_op_vl8re16_v; break;
+ }
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vle16_v; break;
+ case 16: op = rv_op_vle16ff_v; break;
+ }
+ break;
+ case 1: op = rv_op_vluxei16_v; break;
+ case 2: op = rv_op_vlse16_v; break;
+ case 3: op = rv_op_vloxei16_v; break;
+ }
+ break;
+ case 6:
+ switch ((inst >> 20) & 0b111111111111) {
+ case 40: op = rv_op_vl1re32_v; break;
+ case 552: op = rv_op_vl2re32_v; break;
+ case 1576: op = rv_op_vl4re32_v; break;
+ case 3624: op = rv_op_vl8re32_v; break;
+ }
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vle32_v; break;
+ case 16: op = rv_op_vle32ff_v; break;
+ }
+ break;
+ case 1: op = rv_op_vluxei32_v; break;
+ case 2: op = rv_op_vlse32_v; break;
+ case 3: op = rv_op_vloxei32_v; break;
+ }
+ break;
+ case 7:
+ switch ((inst >> 20) & 0b111111111111) {
+ case 40: op = rv_op_vl1re64_v; break;
+ case 552: op = rv_op_vl2re64_v; break;
+ case 1576: op = rv_op_vl4re64_v; break;
+ case 3624: op = rv_op_vl8re64_v; break;
+ }
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vle64_v; break;
+ case 16: op = rv_op_vle64ff_v; break;
+ }
+ break;
+ case 1: op = rv_op_vluxei64_v; break;
+ case 2: op = rv_op_vlse64_v; break;
+ case 3: op = rv_op_vloxei64_v; break;
+ }
+ break;
}
break;
case 3:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fence; break;
case 1: op = rv_op_fence_i; break;
case 2: op = rv_op_lq; break;
}
break;
case 4:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addi; break;
case 1:
- switch (((inst >> 27) & 0b11111)) {
+ switch ((inst >> 27) & 0b11111) {
case 0b00000: op = rv_op_slli; break;
case 0b00001:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0001111: op = rv_op_zip; break;
}
break;
case 0b00010:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_sha256sum0; break;
case 0b0000001: op = rv_op_sha256sum1; break;
case 0b0000010: op = rv_op_sha256sig0; break;
break;
case 0b00101: op = rv_op_bseti; break;
case 0b00110:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_aes64im; break;
default:
if (((inst >> 24) & 0b0111) == 0b001) {
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_clz; break;
case 0b0000001: op = rv_op_ctz; break;
case 0b0000010: op = rv_op_cpop; break;
case 3: op = rv_op_sltiu; break;
case 4: op = rv_op_xori; break;
case 5:
- switch (((inst >> 27) & 0b11111)) {
+ switch ((inst >> 27) & 0b11111) {
case 0b00000: op = rv_op_srli; break;
case 0b00001:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0001111: op = rv_op_unzip; break;
}
break;
break;
case 5: op = rv_op_auipc; break;
case 6:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addiw; break;
case 1:
- switch (((inst >> 25) & 0b1111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_slliw; break;
- case 4: op = rv_op_slli_uw; break;
- case 48:
+ case 2: op = rv_op_slli_uw; break;
+ case 24:
switch ((inst >> 20) & 0b11111) {
case 0b00000: op = rv_op_clzw; break;
case 0b00001: op = rv_op_ctzw; break;
}
break;
case 5:
- switch (((inst >> 25) & 0b1111111)) {
+ switch ((inst >> 25) & 0b1111111) {
case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break;
case 48: op = rv_op_roriw; break;
}
break;
case 8:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_sb; break;
case 1: op = rv_op_sh; break;
case 2: op = rv_op_sw; break;
}
break;
case 9:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b111111111111) {
+ case 40: op = rv_op_vs1r_v; break;
+ case 552: op = rv_op_vs2r_v; break;
+ case 1576: op = rv_op_vs4r_v; break;
+ case 3624: op = rv_op_vs8r_v; break;
+ }
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vse8_v; break;
+ case 11: op = rv_op_vsm_v; break;
+ }
+ break;
+ case 1: op = rv_op_vsuxei8_v; break;
+ case 2: op = rv_op_vsse8_v; break;
+ case 3: op = rv_op_vsoxei8_v; break;
+ }
+ break;
+ case 1: op = rv_op_fsh; break;
case 2: op = rv_op_fsw; break;
case 3: op = rv_op_fsd; break;
case 4: op = rv_op_fsq; break;
+ case 5:
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vse16_v; break;
+ }
+ break;
+ case 1: op = rv_op_vsuxei16_v; break;
+ case 2: op = rv_op_vsse16_v; break;
+ case 3: op = rv_op_vsoxei16_v; break;
+ }
+ break;
+ case 6:
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vse32_v; break;
+ }
+ break;
+ case 1: op = rv_op_vsuxei32_v; break;
+ case 2: op = rv_op_vsse32_v; break;
+ case 3: op = rv_op_vsoxei32_v; break;
+ }
+ break;
+ case 7:
+ switch ((inst >> 26) & 0b111) {
+ case 0:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_vse64_v; break;
+ }
+ break;
+ case 1: op = rv_op_vsuxei64_v; break;
+ case 2: op = rv_op_vsse64_v; break;
+ case 3: op = rv_op_vsoxei64_v; break;
+ }
+ break;
}
break;
case 11:
- switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 24) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 2: op = rv_op_amoadd_w; break;
case 3: op = rv_op_amoadd_d; break;
case 4: op = rv_op_amoadd_q; break;
case 11: op = rv_op_amoswap_d; break;
case 12: op = rv_op_amoswap_q; break;
case 18:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_w; break;
}
break;
case 19:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_d; break;
}
break;
case 20:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_q; break;
}
break;
}
break;
case 12:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_add; break;
case 1: op = rv_op_sll; break;
case 2: op = rv_op_slt; break;
case 45: op = rv_op_minu; break;
case 46: op = rv_op_max; break;
case 47: op = rv_op_maxu; break;
+ case 075: op = rv_op_czero_eqz; break;
+ case 077: op = rv_op_czero_nez; break;
case 130: op = rv_op_sh1add; break;
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
break;
case 13: op = rv_op_lui; break;
case 14:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addw; break;
case 1: op = rv_op_sllw; break;
case 5: op = rv_op_srlw; break;
}
break;
case 16:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fmadd_s; break;
case 1: op = rv_op_fmadd_d; break;
case 3: op = rv_op_fmadd_q; break;
}
break;
case 17:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fmsub_s; break;
case 1: op = rv_op_fmsub_d; break;
case 3: op = rv_op_fmsub_q; break;
}
break;
case 18:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fnmsub_s; break;
case 1: op = rv_op_fnmsub_d; break;
case 3: op = rv_op_fnmsub_q; break;
}
break;
case 19:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fnmadd_s; break;
case 1: op = rv_op_fnmadd_d; break;
case 3: op = rv_op_fnmadd_q; break;
}
break;
case 20:
- switch (((inst >> 25) & 0b1111111)) {
+ switch ((inst >> 25) & 0b1111111) {
case 0: op = rv_op_fadd_s; break;
case 1: op = rv_op_fadd_d; break;
case 3: op = rv_op_fadd_q; break;
case 13: op = rv_op_fdiv_d; break;
case 15: op = rv_op_fdiv_q; break;
case 16:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_s; break;
case 1: op = rv_op_fsgnjn_s; break;
case 2: op = rv_op_fsgnjx_s; break;
}
break;
case 17:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_d; break;
case 1: op = rv_op_fsgnjn_d; break;
case 2: op = rv_op_fsgnjx_d; break;
}
break;
case 19:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_q; break;
case 1: op = rv_op_fsgnjn_q; break;
case 2: op = rv_op_fsgnjx_q; break;
}
break;
case 20:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_s; break;
case 1: op = rv_op_fmax_s; break;
+ case 2: op = rv_op_fminm_s; break;
+ case 3: op = rv_op_fmaxm_s; break;
}
break;
case 21:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_d; break;
case 1: op = rv_op_fmax_d; break;
+ case 2: op = rv_op_fminm_d; break;
+ case 3: op = rv_op_fmaxm_d; break;
}
break;
- case 23:
+ case 22:
switch (((inst >> 12) & 0b111)) {
+ case 2: op = rv_op_fminm_h; break;
+ case 3: op = rv_op_fmaxm_h; break;
+ }
+ break;
+ case 23:
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_q; break;
case 1: op = rv_op_fmax_q; break;
+ case 2: op = rv_op_fminm_q; break;
+ case 3: op = rv_op_fmaxm_q; break;
}
break;
case 32:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 1: op = rv_op_fcvt_s_d; break;
case 3: op = rv_op_fcvt_s_q; break;
+ case 4: op = rv_op_fround_s; break;
+ case 5: op = rv_op_froundnx_s; break;
+ case 6: op = rv_op_fcvt_s_bf16; break;
}
break;
case 33:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_d_s; break;
case 3: op = rv_op_fcvt_d_q; break;
+ case 4: op = rv_op_fround_d; break;
+ case 5: op = rv_op_froundnx_d; break;
}
break;
- case 35:
+ case 34:
switch (((inst >> 20) & 0b11111)) {
+ case 4: op = rv_op_fround_h; break;
+ case 5: op = rv_op_froundnx_h; break;
+ case 8: op = rv_op_fcvt_bf16_s; break;
+ }
+ break;
+ case 35:
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_q_s; break;
case 1: op = rv_op_fcvt_q_d; break;
+ case 4: op = rv_op_fround_q; break;
+ case 5: op = rv_op_froundnx_q; break;
}
break;
case 44:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_s; break;
}
break;
case 45:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_d; break;
}
break;
case 47:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_q; break;
}
break;
case 80:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_s; break;
case 1: op = rv_op_flt_s; break;
case 2: op = rv_op_feq_s; break;
+ case 4: op = rv_op_fleq_s; break;
+ case 5: op = rv_op_fltq_s; break;
}
break;
case 81:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_d; break;
case 1: op = rv_op_flt_d; break;
case 2: op = rv_op_feq_d; break;
+ case 4: op = rv_op_fleq_d; break;
+ case 5: op = rv_op_fltq_d; break;
}
break;
- case 83:
+ case 82:
switch (((inst >> 12) & 0b111)) {
+ case 4: op = rv_op_fleq_h; break;
+ case 5: op = rv_op_fltq_h; break;
+ }
+ break;
+ case 83:
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_q; break;
case 1: op = rv_op_flt_q; break;
case 2: op = rv_op_feq_q; break;
+ case 4: op = rv_op_fleq_q; break;
+ case 5: op = rv_op_fltq_q; break;
+ }
+ break;
+ case 89:
+ switch (((inst >> 12) & 0b111)) {
+ case 0: op = rv_op_fmvp_d_x; break;
+ }
+ break;
+ case 91:
+ switch (((inst >> 12) & 0b111)) {
+ case 0: op = rv_op_fmvp_q_x; break;
}
break;
case 96:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_s; break;
case 1: op = rv_op_fcvt_wu_s; break;
case 2: op = rv_op_fcvt_l_s; break;
}
break;
case 97:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_d; break;
case 1: op = rv_op_fcvt_wu_d; break;
case 2: op = rv_op_fcvt_l_d; break;
case 3: op = rv_op_fcvt_lu_d; break;
+ case 8: op = rv_op_fcvtmod_w_d; break;
}
break;
case 99:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_q; break;
case 1: op = rv_op_fcvt_wu_q; break;
case 2: op = rv_op_fcvt_l_q; break;
}
break;
case 104:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_s_w; break;
case 1: op = rv_op_fcvt_s_wu; break;
case 2: op = rv_op_fcvt_s_l; break;
}
break;
case 105:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_d_w; break;
case 1: op = rv_op_fcvt_d_wu; break;
case 2: op = rv_op_fcvt_d_l; break;
}
break;
case 107:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_q_w; break;
case 1: op = rv_op_fcvt_q_wu; break;
case 2: op = rv_op_fcvt_q_l; break;
}
break;
case 112:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_s; break;
case 1: op = rv_op_fclass_s; break;
}
break;
case 113:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_d; break;
case 1: op = rv_op_fclass_d; break;
+ case 8: op = rv_op_fmvh_x_d; break;
+ }
+ break;
+ case 114:
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
+ case 0: op = rv_op_fmv_x_h; break;
}
break;
case 115:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_q; break;
case 1: op = rv_op_fclass_q; break;
+ case 8: op = rv_op_fmvh_x_q; break;
}
break;
case 120:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_s_x; break;
+ case 8: op = rv_op_fli_s; break;
}
break;
case 121:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_d_x; break;
+ case 8: op = rv_op_fli_d; break;
+ }
+ break;
+ case 122:
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
+ case 0: op = rv_op_fmv_h_x; break;
+ case 8: op = rv_op_fli_h; break;
}
break;
case 123:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_q_x; break;
+ case 8: op = rv_op_fli_q; break;
+ }
+ break;
+ }
+ break;
+ case 21:
+ switch ((inst >> 12) & 0b111) {
+ case 0:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vadd_vv; break;
+ case 1: op = rv_op_vandn_vv; break;
+ case 2: op = rv_op_vsub_vv; break;
+ case 4: op = rv_op_vminu_vv; break;
+ case 5: op = rv_op_vmin_vv; break;
+ case 6: op = rv_op_vmaxu_vv; break;
+ case 7: op = rv_op_vmax_vv; break;
+ case 9: op = rv_op_vand_vv; break;
+ case 10: op = rv_op_vor_vv; break;
+ case 11: op = rv_op_vxor_vv; break;
+ case 12: op = rv_op_vrgather_vv; break;
+ case 14: op = rv_op_vrgatherei16_vv; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vvm;
+ }
+ break;
+ case 17: op = rv_op_vmadc_vvm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vvm;
+ }
+ break;
+ case 19: op = rv_op_vmsbc_vvm; break;
+ case 20: op = rv_op_vror_vv; break;
+ case 21: op = rv_op_vrol_vv; break;
+ case 23:
+ if (((inst >> 20) & 0b111111) == 32)
+ op = rv_op_vmv_v_v;
+ else if (((inst >> 25) & 1) == 0)
+ op = rv_op_vmerge_vvm;
+ break;
+ case 24: op = rv_op_vmseq_vv; break;
+ case 25: op = rv_op_vmsne_vv; break;
+ case 26: op = rv_op_vmsltu_vv; break;
+ case 27: op = rv_op_vmslt_vv; break;
+ case 28: op = rv_op_vmsleu_vv; break;
+ case 29: op = rv_op_vmsle_vv; break;
+ case 32: op = rv_op_vsaddu_vv; break;
+ case 33: op = rv_op_vsadd_vv; break;
+ case 34: op = rv_op_vssubu_vv; break;
+ case 35: op = rv_op_vssub_vv; break;
+ case 37: op = rv_op_vsll_vv; break;
+ case 39: op = rv_op_vsmul_vv; break;
+ case 40: op = rv_op_vsrl_vv; break;
+ case 41: op = rv_op_vsra_vv; break;
+ case 42: op = rv_op_vssrl_vv; break;
+ case 43: op = rv_op_vssra_vv; break;
+ case 44: op = rv_op_vnsrl_wv; break;
+ case 45: op = rv_op_vnsra_wv; break;
+ case 46: op = rv_op_vnclipu_wv; break;
+ case 47: op = rv_op_vnclip_wv; break;
+ case 48: op = rv_op_vwredsumu_vs; break;
+ case 49: op = rv_op_vwredsum_vs; break;
+ case 53: op = rv_op_vwsll_vv; break;
+ }
+ break;
+ case 1:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vfadd_vv; break;
+ case 1: op = rv_op_vfredusum_vs; break;
+ case 2: op = rv_op_vfsub_vv; break;
+ case 3: op = rv_op_vfredosum_vs; break;
+ case 4: op = rv_op_vfmin_vv; break;
+ case 5: op = rv_op_vfredmin_vs; break;
+ case 6: op = rv_op_vfmax_vv; break;
+ case 7: op = rv_op_vfredmax_vs; break;
+ case 8: op = rv_op_vfsgnj_vv; break;
+ case 9: op = rv_op_vfsgnjn_vv; break;
+ case 10: op = rv_op_vfsgnjx_vv; break;
+ case 16:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
+ }
+ break;
+ case 18:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vfcvt_xu_f_v; break;
+ case 1: op = rv_op_vfcvt_x_f_v; break;
+ case 2: op = rv_op_vfcvt_f_xu_v; break;
+ case 3: op = rv_op_vfcvt_f_x_v; break;
+ case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
+ case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
+ case 8: op = rv_op_vfwcvt_xu_f_v; break;
+ case 9: op = rv_op_vfwcvt_x_f_v; break;
+ case 10: op = rv_op_vfwcvt_f_xu_v; break;
+ case 11: op = rv_op_vfwcvt_f_x_v; break;
+ case 12: op = rv_op_vfwcvt_f_f_v; break;
+ case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
+ case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
+ case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
+ case 16: op = rv_op_vfncvt_xu_f_w; break;
+ case 17: op = rv_op_vfncvt_x_f_w; break;
+ case 18: op = rv_op_vfncvt_f_xu_w; break;
+ case 19: op = rv_op_vfncvt_f_x_w; break;
+ case 20: op = rv_op_vfncvt_f_f_w; break;
+ case 21: op = rv_op_vfncvt_rod_f_f_w; break;
+ case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
+ case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
+ case 29: op = rv_op_vfncvtbf16_f_f_w; break;
+ }
+ break;
+ case 19:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vfsqrt_v; break;
+ case 4: op = rv_op_vfrsqrt7_v; break;
+ case 5: op = rv_op_vfrec7_v; break;
+ case 16: op = rv_op_vfclass_v; break;
+ }
+ break;
+ case 24: op = rv_op_vmfeq_vv; break;
+ case 25: op = rv_op_vmfle_vv; break;
+ case 27: op = rv_op_vmflt_vv; break;
+ case 28: op = rv_op_vmfne_vv; break;
+ case 32: op = rv_op_vfdiv_vv; break;
+ case 36: op = rv_op_vfmul_vv; break;
+ case 40: op = rv_op_vfmadd_vv; break;
+ case 41: op = rv_op_vfnmadd_vv; break;
+ case 42: op = rv_op_vfmsub_vv; break;
+ case 43: op = rv_op_vfnmsub_vv; break;
+ case 44: op = rv_op_vfmacc_vv; break;
+ case 45: op = rv_op_vfnmacc_vv; break;
+ case 46: op = rv_op_vfmsac_vv; break;
+ case 47: op = rv_op_vfnmsac_vv; break;
+ case 48: op = rv_op_vfwadd_vv; break;
+ case 49: op = rv_op_vfwredusum_vs; break;
+ case 50: op = rv_op_vfwsub_vv; break;
+ case 51: op = rv_op_vfwredosum_vs; break;
+ case 52: op = rv_op_vfwadd_wv; break;
+ case 54: op = rv_op_vfwsub_wv; break;
+ case 56: op = rv_op_vfwmul_vv; break;
+ case 59: op = rv_op_vfwmaccbf16_vv; break;
+ case 60: op = rv_op_vfwmacc_vv; break;
+ case 61: op = rv_op_vfwnmacc_vv; break;
+ case 62: op = rv_op_vfwmsac_vv; break;
+ case 63: op = rv_op_vfwnmsac_vv; break;
+ }
+ break;
+ case 2:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vredsum_vs; break;
+ case 1: op = rv_op_vredand_vs; break;
+ case 2: op = rv_op_vredor_vs; break;
+ case 3: op = rv_op_vredxor_vs; break;
+ case 4: op = rv_op_vredminu_vs; break;
+ case 5: op = rv_op_vredmin_vs; break;
+ case 6: op = rv_op_vredmaxu_vs; break;
+ case 7: op = rv_op_vredmax_vs; break;
+ case 8: op = rv_op_vaaddu_vv; break;
+ case 9: op = rv_op_vaadd_vv; break;
+ case 10: op = rv_op_vasubu_vv; break;
+ case 11: op = rv_op_vasub_vv; break;
+ case 12: op = rv_op_vclmul_vv; break;
+ case 13: op = rv_op_vclmulh_vv; break;
+ case 16:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
+ case 16: op = rv_op_vcpop_m; break;
+ case 17: op = rv_op_vfirst_m; break;
+ }
+ break;
+ case 18:
+ switch ((inst >> 15) & 0b11111) {
+ case 2: op = rv_op_vzext_vf8; break;
+ case 3: op = rv_op_vsext_vf8; break;
+ case 4: op = rv_op_vzext_vf4; break;
+ case 5: op = rv_op_vsext_vf4; break;
+ case 6: op = rv_op_vzext_vf2; break;
+ case 7: op = rv_op_vsext_vf2; break;
+ case 8: op = rv_op_vbrev8_v; break;
+ case 9: op = rv_op_vrev8_v; break;
+ case 10: op = rv_op_vbrev_v; break;
+ case 12: op = rv_op_vclz_v; break;
+ case 13: op = rv_op_vctz_v; break;
+ case 14: op = rv_op_vcpop_v; break;
+ }
+ break;
+ case 20:
+ switch ((inst >> 15) & 0b11111) {
+ case 1: op = rv_op_vmsbf_m; break;
+ case 2: op = rv_op_vmsof_m; break;
+ case 3: op = rv_op_vmsif_m; break;
+ case 16: op = rv_op_viota_m; break;
+ case 17:
+ if (((inst >> 20) & 0b11111) == 0) {
+ op = rv_op_vid_v;
+ }
+ break;
+ }
+ break;
+ case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
+ case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
+ case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
+ case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
+ case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
+ case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
+ case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
+ case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
+ case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
+ case 32: op = rv_op_vdivu_vv; break;
+ case 33: op = rv_op_vdiv_vv; break;
+ case 34: op = rv_op_vremu_vv; break;
+ case 35: op = rv_op_vrem_vv; break;
+ case 36: op = rv_op_vmulhu_vv; break;
+ case 37: op = rv_op_vmul_vv; break;
+ case 38: op = rv_op_vmulhsu_vv; break;
+ case 39: op = rv_op_vmulh_vv; break;
+ case 41: op = rv_op_vmadd_vv; break;
+ case 43: op = rv_op_vnmsub_vv; break;
+ case 45: op = rv_op_vmacc_vv; break;
+ case 47: op = rv_op_vnmsac_vv; break;
+ case 48: op = rv_op_vwaddu_vv; break;
+ case 49: op = rv_op_vwadd_vv; break;
+ case 50: op = rv_op_vwsubu_vv; break;
+ case 51: op = rv_op_vwsub_vv; break;
+ case 52: op = rv_op_vwaddu_wv; break;
+ case 53: op = rv_op_vwadd_wv; break;
+ case 54: op = rv_op_vwsubu_wv; break;
+ case 55: op = rv_op_vwsub_wv; break;
+ case 56: op = rv_op_vwmulu_vv; break;
+ case 58: op = rv_op_vwmulsu_vv; break;
+ case 59: op = rv_op_vwmul_vv; break;
+ case 60: op = rv_op_vwmaccu_vv; break;
+ case 61: op = rv_op_vwmacc_vv; break;
+ case 63: op = rv_op_vwmaccsu_vv; break;
+ }
+ break;
+ case 3:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vadd_vi; break;
+ case 3: op = rv_op_vrsub_vi; break;
+ case 9: op = rv_op_vand_vi; break;
+ case 10: op = rv_op_vor_vi; break;
+ case 11: op = rv_op_vxor_vi; break;
+ case 12: op = rv_op_vrgather_vi; break;
+ case 14: op = rv_op_vslideup_vi; break;
+ case 15: op = rv_op_vslidedown_vi; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vim;
+ }
+ break;
+ case 17: op = rv_op_vmadc_vim; break;
+ case 20: case 21: op = rv_op_vror_vi; break;
+ case 23:
+ if (((inst >> 20) & 0b111111) == 32)
+ op = rv_op_vmv_v_i;
+ else if (((inst >> 25) & 1) == 0)
+ op = rv_op_vmerge_vim;
+ break;
+ case 24: op = rv_op_vmseq_vi; break;
+ case 25: op = rv_op_vmsne_vi; break;
+ case 28: op = rv_op_vmsleu_vi; break;
+ case 29: op = rv_op_vmsle_vi; break;
+ case 30: op = rv_op_vmsgtu_vi; break;
+ case 31: op = rv_op_vmsgt_vi; break;
+ case 32: op = rv_op_vsaddu_vi; break;
+ case 33: op = rv_op_vsadd_vi; break;
+ case 37: op = rv_op_vsll_vi; break;
+ case 39:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vmv1r_v; break;
+ case 1: op = rv_op_vmv2r_v; break;
+ case 3: op = rv_op_vmv4r_v; break;
+ case 7: op = rv_op_vmv8r_v; break;
+ }
+ break;
+ case 40: op = rv_op_vsrl_vi; break;
+ case 41: op = rv_op_vsra_vi; break;
+ case 42: op = rv_op_vssrl_vi; break;
+ case 43: op = rv_op_vssra_vi; break;
+ case 44: op = rv_op_vnsrl_wi; break;
+ case 45: op = rv_op_vnsra_wi; break;
+ case 46: op = rv_op_vnclipu_wi; break;
+ case 47: op = rv_op_vnclip_wi; break;
+ case 53: op = rv_op_vwsll_vi; break;
+ }
+ break;
+ case 4:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vadd_vx; break;
+ case 1: op = rv_op_vandn_vx; break;
+ case 2: op = rv_op_vsub_vx; break;
+ case 3: op = rv_op_vrsub_vx; break;
+ case 4: op = rv_op_vminu_vx; break;
+ case 5: op = rv_op_vmin_vx; break;
+ case 6: op = rv_op_vmaxu_vx; break;
+ case 7: op = rv_op_vmax_vx; break;
+ case 9: op = rv_op_vand_vx; break;
+ case 10: op = rv_op_vor_vx; break;
+ case 11: op = rv_op_vxor_vx; break;
+ case 12: op = rv_op_vrgather_vx; break;
+ case 14: op = rv_op_vslideup_vx; break;
+ case 15: op = rv_op_vslidedown_vx; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vxm;
+ }
+ break;
+ case 17: op = rv_op_vmadc_vxm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vxm;
+ }
+ break;
+ case 19: op = rv_op_vmsbc_vxm; break;
+ case 20: op = rv_op_vror_vx; break;
+ case 21: op = rv_op_vrol_vx; break;
+ case 23:
+ if (((inst >> 20) & 0b111111) == 32)
+ op = rv_op_vmv_v_x;
+ else if (((inst >> 25) & 1) == 0)
+ op = rv_op_vmerge_vxm;
+ break;
+ case 24: op = rv_op_vmseq_vx; break;
+ case 25: op = rv_op_vmsne_vx; break;
+ case 26: op = rv_op_vmsltu_vx; break;
+ case 27: op = rv_op_vmslt_vx; break;
+ case 28: op = rv_op_vmsleu_vx; break;
+ case 29: op = rv_op_vmsle_vx; break;
+ case 30: op = rv_op_vmsgtu_vx; break;
+ case 31: op = rv_op_vmsgt_vx; break;
+ case 32: op = rv_op_vsaddu_vx; break;
+ case 33: op = rv_op_vsadd_vx; break;
+ case 34: op = rv_op_vssubu_vx; break;
+ case 35: op = rv_op_vssub_vx; break;
+ case 37: op = rv_op_vsll_vx; break;
+ case 39: op = rv_op_vsmul_vx; break;
+ case 40: op = rv_op_vsrl_vx; break;
+ case 41: op = rv_op_vsra_vx; break;
+ case 42: op = rv_op_vssrl_vx; break;
+ case 43: op = rv_op_vssra_vx; break;
+ case 44: op = rv_op_vnsrl_wx; break;
+ case 45: op = rv_op_vnsra_wx; break;
+ case 46: op = rv_op_vnclipu_wx; break;
+ case 47: op = rv_op_vnclip_wx; break;
+ case 53: op = rv_op_vwsll_vx; break;
+ }
+ break;
+ case 5:
+ switch ((inst >> 26) & 0b111111) {
+ case 0: op = rv_op_vfadd_vf; break;
+ case 2: op = rv_op_vfsub_vf; break;
+ case 4: op = rv_op_vfmin_vf; break;
+ case 6: op = rv_op_vfmax_vf; break;
+ case 8: op = rv_op_vfsgnj_vf; break;
+ case 9: op = rv_op_vfsgnjn_vf; break;
+ case 10: op = rv_op_vfsgnjx_vf; break;
+ case 14: op = rv_op_vfslide1up_vf; break;
+ case 15: op = rv_op_vfslide1down_vf; break;
+ case 16:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
+ }
+ break;
+ case 23:
+ if (((inst >> 25) & 1) == 0)
+ op = rv_op_vfmerge_vfm;
+ else if (((inst >> 20) & 0b111111) == 32)
+ op = rv_op_vfmv_v_f;
+ break;
+ case 24: op = rv_op_vmfeq_vf; break;
+ case 25: op = rv_op_vmfle_vf; break;
+ case 27: op = rv_op_vmflt_vf; break;
+ case 28: op = rv_op_vmfne_vf; break;
+ case 29: op = rv_op_vmfgt_vf; break;
+ case 31: op = rv_op_vmfge_vf; break;
+ case 32: op = rv_op_vfdiv_vf; break;
+ case 33: op = rv_op_vfrdiv_vf; break;
+ case 36: op = rv_op_vfmul_vf; break;
+ case 39: op = rv_op_vfrsub_vf; break;
+ case 40: op = rv_op_vfmadd_vf; break;
+ case 41: op = rv_op_vfnmadd_vf; break;
+ case 42: op = rv_op_vfmsub_vf; break;
+ case 43: op = rv_op_vfnmsub_vf; break;
+ case 44: op = rv_op_vfmacc_vf; break;
+ case 45: op = rv_op_vfnmacc_vf; break;
+ case 46: op = rv_op_vfmsac_vf; break;
+ case 47: op = rv_op_vfnmsac_vf; break;
+ case 48: op = rv_op_vfwadd_vf; break;
+ case 50: op = rv_op_vfwsub_vf; break;
+ case 52: op = rv_op_vfwadd_wf; break;
+ case 54: op = rv_op_vfwsub_wf; break;
+ case 56: op = rv_op_vfwmul_vf; break;
+ case 59: op = rv_op_vfwmaccbf16_vf; break;
+ case 60: op = rv_op_vfwmacc_vf; break;
+ case 61: op = rv_op_vfwnmacc_vf; break;
+ case 62: op = rv_op_vfwmsac_vf; break;
+ case 63: op = rv_op_vfwnmsac_vf; break;
+ }
+ break;
+ case 6:
+ switch ((inst >> 26) & 0b111111) {
+ case 8: op = rv_op_vaaddu_vx; break;
+ case 9: op = rv_op_vaadd_vx; break;
+ case 10: op = rv_op_vasubu_vx; break;
+ case 11: op = rv_op_vasub_vx; break;
+ case 12: op = rv_op_vclmul_vx; break;
+ case 13: op = rv_op_vclmulh_vx; break;
+ case 14: op = rv_op_vslide1up_vx; break;
+ case 15: op = rv_op_vslide1down_vx; break;
+ case 16:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
+ }
+ break;
+ case 32: op = rv_op_vdivu_vx; break;
+ case 33: op = rv_op_vdiv_vx; break;
+ case 34: op = rv_op_vremu_vx; break;
+ case 35: op = rv_op_vrem_vx; break;
+ case 36: op = rv_op_vmulhu_vx; break;
+ case 37: op = rv_op_vmul_vx; break;
+ case 38: op = rv_op_vmulhsu_vx; break;
+ case 39: op = rv_op_vmulh_vx; break;
+ case 41: op = rv_op_vmadd_vx; break;
+ case 43: op = rv_op_vnmsub_vx; break;
+ case 45: op = rv_op_vmacc_vx; break;
+ case 47: op = rv_op_vnmsac_vx; break;
+ case 48: op = rv_op_vwaddu_vx; break;
+ case 49: op = rv_op_vwadd_vx; break;
+ case 50: op = rv_op_vwsubu_vx; break;
+ case 51: op = rv_op_vwsub_vx; break;
+ case 52: op = rv_op_vwaddu_wx; break;
+ case 53: op = rv_op_vwadd_wx; break;
+ case 54: op = rv_op_vwsubu_wx; break;
+ case 55: op = rv_op_vwsub_wx; break;
+ case 56: op = rv_op_vwmulu_vx; break;
+ case 58: op = rv_op_vwmulsu_vx; break;
+ case 59: op = rv_op_vwmul_vx; break;
+ case 60: op = rv_op_vwmaccu_vx; break;
+ case 61: op = rv_op_vwmacc_vx; break;
+ case 62: op = rv_op_vwmaccus_vx; break;
+ case 63: op = rv_op_vwmaccsu_vx; break;
+ }
+ break;
+ case 7:
+ if (((inst >> 31) & 1) == 0) {
+ op = rv_op_vsetvli;
+ } else if ((inst >> 30) & 1) {
+ op = rv_op_vsetivli;
+ } else if (((inst >> 25) & 0b11111) == 0) {
+ op = rv_op_vsetvl;
}
break;
}
break;
case 22:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addid; break;
case 1:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_sllid; break;
}
break;
case 5:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_srlid; break;
case 16: op = rv_op_sraid; break;
}
}
break;
case 24:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_beq; break;
case 1: op = rv_op_bne; break;
case 4: op = rv_op_blt; break;
}
break;
case 25:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_jalr; break;
}
break;
case 27: op = rv_op_jal; break;
case 28:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
+ switch (((inst >> 20) & 0b111111100000) |
+ ((inst >> 7) & 0b000000011111)) {
case 0:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 0: op = rv_op_ecall; break;
case 32: op = rv_op_ebreak; break;
case 64: op = rv_op_uret; break;
}
break;
case 256:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 2:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_sret; break;
}
break;
case 4: op = rv_op_sfence_vm; break;
case 5:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_wfi; break;
}
break;
break;
case 288: op = rv_op_sfence_vma; break;
case 512:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 64: op = rv_op_hret; break;
}
break;
case 768:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 64: op = rv_op_mret; break;
}
break;
case 1952:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 576: op = rv_op_dret; break;
}
break;
case 7: op = rv_op_csrrci; break;
}
break;
+ case 29:
+ if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
+ switch ((inst >> 26) & 0b111111) {
+ case 32: op = rv_op_vsm3me_vv; break;
+ case 33: op = rv_op_vsm4k_vi; break;
+ case 34: op = rv_op_vaeskf1_vi; break;
+ case 40:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vaesdm_vv; break;
+ case 1: op = rv_op_vaesdf_vv; break;
+ case 2: op = rv_op_vaesem_vv; break;
+ case 3: op = rv_op_vaesef_vv; break;
+ case 16: op = rv_op_vsm4r_vv; break;
+ case 17: op = rv_op_vgmul_vv; break;
+ }
+ break;
+ case 41:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vaesdm_vs; break;
+ case 1: op = rv_op_vaesdf_vs; break;
+ case 2: op = rv_op_vaesem_vs; break;
+ case 3: op = rv_op_vaesef_vs; break;
+ case 7: op = rv_op_vaesz_vs; break;
+ case 16: op = rv_op_vsm4r_vs; break;
+ }
+ break;
+ case 42: op = rv_op_vaeskf2_vi; break;
+ case 43: op = rv_op_vsm3c_vi; break;
+ case 44: op = rv_op_vghsh_vv; break;
+ case 45: op = rv_op_vsha2ms_vv; break;
+ case 46: op = rv_op_vsha2ch_vv; break;
+ case 47: op = rv_op_vsha2cl_vv; break;
+ }
+ }
+ break;
case 30:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addd; break;
case 1: op = rv_op_slld; break;
case 5: op = rv_op_srld; break;
return (inst << 59) >> 61;
}
+static uint32_t calculate_xreg(uint32_t sreg)
+{
+ return sreg < 2 ? sreg + 8 : sreg + 16;
+}
+
+static uint32_t operand_sreg1(rv_inst inst)
+{
+ return calculate_xreg((inst << 54) >> 61);
+}
+
+static uint32_t operand_sreg2(rv_inst inst)
+{
+ return calculate_xreg((inst << 59) >> 61);
+}
+
static uint32_t operand_crd(rv_inst inst)
{
return (inst << 52) >> 59;
((inst << 57) >> 62) << 6;
}
+static uint32_t operand_vimm(rv_inst inst)
+{
+ return (int64_t)(inst << 44) >> 59;
+}
+
+static uint32_t operand_vzimm11(rv_inst inst)
+{
+ return (inst << 33) >> 53;
+}
+
+static uint32_t operand_vzimm10(rv_inst inst)
+{
+ return (inst << 34) >> 54;
+}
+
+static uint32_t operand_vzimm6(rv_inst inst)
+{
+ return ((inst << 37) >> 63) << 5 |
+ ((inst << 44) >> 59);
+}
+
static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
return (inst << 40) >> 60;
}
+static uint32_t operand_vm(rv_inst inst)
+{
+ return (inst << 38) >> 63;
+}
+
+static uint32_t operand_uimm_c_lb(rv_inst inst)
+{
+ return (((inst << 58) >> 63) << 1) |
+ ((inst << 57) >> 63);
+}
+
+static uint32_t operand_uimm_c_lh(rv_inst inst)
+{
+ return (((inst << 58) >> 63) << 1);
+}
+
+static uint32_t operand_zcmp_spimm(rv_inst inst)
+{
+ return ((inst << 60) >> 62) << 4;
+}
+
+static uint32_t operand_zcmp_rlist(rv_inst inst)
+{
+ return ((inst << 56) >> 60);
+}
+
+static uint32_t operand_imm6(rv_inst inst)
+{
+ return (inst << 38) >> 60;
+}
+
+static uint32_t operand_imm2(rv_inst inst)
+{
+ return (inst << 37) >> 62;
+}
+
+static uint32_t operand_immh(rv_inst inst)
+{
+ return (inst << 32) >> 58;
+}
+
+static uint32_t operand_imml(rv_inst inst)
+{
+ return (inst << 38) >> 58;
+}
+
+static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
+{
+ int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
+ int regs = rlist == 15 ? 13 : rlist - 3;
+ uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
+ return stack_adj_base + spimm;
+}
+
+static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
+{
+ return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
+ operand_zcmp_spimm(inst));
+}
+
+static uint32_t operand_tbl_index(rv_inst inst)
+{
+ return ((inst << 54) >> 56);
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
rv_inst inst = dec->inst;
dec->codec = opcode_data[dec->op].codec;
switch (dec->codec) {
dec->rs1 = operand_rs1(inst);
dec->rnum = operand_rnum(inst);
break;
+ case rv_codec_v_r:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->vm = operand_vm(inst);
+ break;
+ case rv_codec_v_ldst:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->vm = operand_vm(inst);
+ break;
+ case rv_codec_v_i:
+ dec->rd = operand_rd(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_vimm(inst);
+ dec->vm = operand_vm(inst);
+ break;
+ case rv_codec_vror_vi:
+ dec->rd = operand_rd(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_vzimm6(inst);
+ dec->vm = operand_vm(inst);
+ break;
+ case rv_codec_vsetvli:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->vzimm = operand_vzimm11(inst);
+ break;
+ case rv_codec_vsetivli:
+ dec->rd = operand_rd(inst);
+ dec->imm = operand_vimm(inst);
+ dec->vzimm = operand_vzimm10(inst);
+ break;
+ case rv_codec_zcb_lb:
+ dec->rs1 = operand_crs1q(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ dec->imm = operand_uimm_c_lb(inst);
+ break;
+ case rv_codec_zcb_lh:
+ dec->rs1 = operand_crs1q(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ dec->imm = operand_uimm_c_lh(inst);
+ break;
+ case rv_codec_zcb_ext:
+ dec->rd = operand_crs1q(inst) + 8;
+ break;
+ case rv_codec_zcb_mul:
+ dec->rd = operand_crs1rdq(inst) + 8;
+ dec->rs2 = operand_crs2q(inst) + 8;
+ break;
+ case rv_codec_zcmp_cm_pushpop:
+ dec->imm = operand_zcmp_stack_adj(inst, isa);
+ dec->rlist = operand_zcmp_rlist(inst);
+ break;
+ case rv_codec_zcmp_cm_mv:
+ dec->rd = operand_sreg1(inst);
+ dec->rs2 = operand_sreg2(inst);
+ break;
+ case rv_codec_zcmt_jt:
+ dec->imm = operand_tbl_index(inst);
+ break;
+ case rv_codec_fli:
+ dec->rd = operand_rd(inst);
+ dec->imm = operand_rs1(inst);
+ break;
+ case rv_codec_r2_imm5:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->imm = operand_rs2(inst);
+ break;
+ case rv_codec_r2:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ break;
+ case rv_codec_r2_imm6:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->imm = operand_imm6(inst);
+ break;
+ case rv_codec_r_imm2:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_imm2(inst);
+ break;
+ case rv_codec_r2_immhl:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->imm = operand_immh(inst);
+ dec->imm1 = operand_imml(inst);
+ break;
+ case rv_codec_r2_imm2_imm5:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->imm = sextract32(operand_rs2(inst), 0, 5);
+ dec->imm1 = operand_imm2(inst);
+ break;
};
}
{
/* NOTE: supports maximum instruction size of 64-bits */
- /* instruction length coding
+ /*
+ * instruction length coding
*
* aa - 16 bit aa != 11
* bbb11 - 32 bit bbb != 111
static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
char tmp[64];
const char *fmt;
case ')':
append(buf, ")", buflen);
break;
+ case '-':
+ append(buf, "-", buflen);
+ break;
case 'b':
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
append(buf, tmp, buflen);
append(buf, rv_ireg_name_sym[dec->rs2], buflen);
break;
case '3':
- append(buf, rv_freg_name_sym[dec->rd], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
+ rv_freg_name_sym[dec->rd],
+ buflen);
break;
case '4':
- append(buf, rv_freg_name_sym[dec->rs1], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
+ rv_freg_name_sym[dec->rs1],
+ buflen);
break;
case '5':
- append(buf, rv_freg_name_sym[dec->rs2], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
+ rv_freg_name_sym[dec->rs2],
+ buflen);
break;
case '6':
- append(buf, rv_freg_name_sym[dec->rs3], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
+ rv_freg_name_sym[dec->rs3],
+ buflen);
break;
case '7':
snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
snprintf(tmp, sizeof(tmp), "%d", dec->imm);
append(buf, tmp, buflen);
break;
+ case 'u':
+ snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111));
+ append(buf, tmp, buflen);
+ break;
+ case 'j':
+ snprintf(tmp, sizeof(tmp), "%d", dec->imm1);
+ append(buf, tmp, buflen);
+ break;
case 'o':
snprintf(tmp, sizeof(tmp), "%d", dec->imm);
append(buf, tmp, buflen);
dec->pc + dec->imm);
append(buf, tmp, buflen);
break;
+ case 'U':
+ fmt++;
+ snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12);
+ append(buf, tmp, buflen);
+ if (*fmt == 'o') {
+ while (strlen(buf) < tab * 2) {
+ append(buf, " ", buflen);
+ }
+ snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
+ dec->pc + dec->imm);
+ append(buf, tmp, buflen);
+ }
+ break;
case 'c': {
const char *name = csr_name(dec->imm & 0xfff);
if (name) {
append(buf, ".rl", buflen);
}
break;
+ case 'l':
+ append(buf, ",v0", buflen);
+ break;
+ case 'm':
+ if (dec->vm == 0) {
+ append(buf, ",v0.t", buflen);
+ }
+ break;
+ case 'D':
+ append(buf, rv_vreg_name_sym[dec->rd], buflen);
+ break;
+ case 'E':
+ append(buf, rv_vreg_name_sym[dec->rs1], buflen);
+ break;
+ case 'F':
+ append(buf, rv_vreg_name_sym[dec->rs2], buflen);
+ break;
+ case 'G':
+ append(buf, rv_vreg_name_sym[dec->rs3], buflen);
+ break;
+ case 'v': {
+ char nbuf[32] = {0};
+ const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
+ sprintf(nbuf, "%d", sew);
+ const int lmul = dec->vzimm & 0b11;
+ const int flmul = (dec->vzimm >> 2) & 1;
+ const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
+ const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
+ append(buf, "e", buflen);
+ append(buf, nbuf, buflen);
+ append(buf, ",m", buflen);
+ if (flmul) {
+ switch (lmul) {
+ case 3:
+ sprintf(nbuf, "f2");
+ break;
+ case 2:
+ sprintf(nbuf, "f4");
+ break;
+ case 1:
+ sprintf(nbuf, "f8");
+ break;
+ }
+ append(buf, nbuf, buflen);
+ } else {
+ sprintf(nbuf, "%d", 1 << lmul);
+ append(buf, nbuf, buflen);
+ }
+ append(buf, ",", buflen);
+ append(buf, vta, buflen);
+ append(buf, ",", buflen);
+ append(buf, vma, buflen);
+ break;
+ }
+ case 'x': {
+ switch (dec->rlist) {
+ case 4:
+ snprintf(tmp, sizeof(tmp), "{ra}");
+ break;
+ case 5:
+ snprintf(tmp, sizeof(tmp), "{ra, s0}");
+ break;
+ case 15:
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
+ break;
+ default:
+ snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
+ break;
+ }
+ append(buf, tmp, buflen);
+ break;
+ }
+ case 'h':
+ append(buf, rv_fli_name_const[dec->imm], buflen);
+ break;
default:
break;
}
static void decode_inst_lift_pseudo(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
if (!comp_data) {
return;
static void decode_inst_decompress_rv32(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv32;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
static void decode_inst_decompress_rv64(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv64;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
static void decode_inst_decompress_rv128(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv128;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
/* disassemble instruction */
static void
-disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
+disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
+ RISCVCPUConfig *cfg)
{
rv_decode dec = { 0 };
dec.pc = pc;
dec.inst = inst;
- decode_inst_opcode(&dec, isa);
+ dec.cfg = cfg;
+
+ static const struct {
+ bool (*guard_func)(const RISCVCPUConfig *);
+ const rv_opcode_data *opcode_data;
+ void (*decode_func)(rv_decode *, rv_isa);
+ } decoders[] = {
+ { always_true_p, rvi_opcode_data, decode_inst_opcode },
+ { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
+ { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
+ { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
+ { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
+ { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
+ { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
+ { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
+ { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
+ { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
+ { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
+ { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
+ { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
+ bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
+ const rv_opcode_data *opcode_data = decoders[i].opcode_data;
+ void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
+
+ if (guard_func(cfg)) {
+ dec.opcode_data = opcode_data;
+ decode_func(&dec, isa);
+ if (dec.op != rv_op_illegal)
+ break;
+ }
+ }
+
+ if (dec.op == rv_op_illegal) {
+ dec.opcode_data = rvi_opcode_data;
+ }
+
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
decode_inst_lift_pseudo(&dec);
- format_inst(buf, buflen, 16, &dec);
+ format_inst(buf, buflen, 24, &dec);
}
#define INST_FMT_2 "%04" PRIx64 " "
break;
}
- disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
+ disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
+ (RISCVCPUConfig *)info->target_info);
(*info->fprintf_func)(info->stream, "%s", buf);
return len;
projects / mirror_qemu.git / blobdiff