agp/intel: Add actual definitions of the Sandybridge PTE caching bits.

[mirror_ubuntu-artful-kernel.git] / drivers / char / agp / intel-gtt.c

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index e8ea6825822ce8ccb04f25a444c7880b1b6da170..ccd4b1e694d17b450aa4ee67fc2f51dc737939fe 100644 (file)
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -176,7 +176,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
        if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
            agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
        {
-               cache_bits = I830_PTE_SYSTEM_CACHED;
+               cache_bits = GEN6_PTE_LLC_MLC;
        }
 
        for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -797,6 +797,10 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 
        /* we have to call this as early as possible after the MMIO base address is known */
        intel_i830_init_gtt_entries();
+       if (intel_private.gtt_entries == 0) {
+               iounmap(intel_private.registers);
+               return -ENOMEM;
+       }
 
        agp_bridge->gatt_table = NULL;
 
@@ -1059,7 +1063,7 @@ static void intel_i9xx_setup_flush(void)
        }
 }
 
-static int intel_i915_configure(void)
+static int intel_i9xx_configure(void)
 {
        struct aper_size_info_fixed *current_size;
        u32 temp;
@@ -1207,6 +1211,38 @@ static int intel_i9xx_fetch_size(void)
        return 0;
 }
 
+static int intel_i915_get_gtt_size(void)
+{
+       int size;
+
+       if (IS_G33) {
+               u16 gmch_ctrl;
+
+               /* G33's GTT size defined in gmch_ctrl */
+               pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
+               switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
+               case G33_PGETBL_SIZE_1M:
+                       size = 1024;
+                       break;
+               case G33_PGETBL_SIZE_2M:
+                       size = 2048;
+                       break;
+               default:
+                       dev_info(&agp_bridge->dev->dev,
+                                "unknown page table size 0x%x, assuming 512KB\n",
+                               (gmch_ctrl & G33_PGETBL_SIZE_MASK));
+                       size = 512;
+               }
+       } else {
+               /* On previous hardware, the GTT size was just what was
+                * required to map the aperture.
+                */
+               size = agp_bridge->driver->fetch_size();
+       }
+
+       return KB(size);
+}
+
 /* The intel i915 automatically initializes the agp aperture during POST.
  * Use the memory already set aside for in the GTT.
  */
@@ -1216,7 +1252,7 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
        struct aper_size_info_fixed *size;
        int num_entries;
        u32 temp, temp2;
-       int gtt_map_size = 256 * 1024;
+       int gtt_map_size;
 
        size = agp_bridge->current_size;
        page_order = size->page_order;
@@ -1226,8 +1262,8 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
        pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
 
-       if (IS_G33)
-           gtt_map_size = 1024 * 1024; /* 1M on G33 */
+       gtt_map_size = intel_i915_get_gtt_size();
+
        intel_private.gtt = ioremap(temp2, gtt_map_size);
        if (!intel_private.gtt)
                return -ENOMEM;
@@ -1247,6 +1283,11 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 
        /* we have to call this as early as possible after the MMIO base address is known */
        intel_i830_init_gtt_entries();
+       if (intel_private.gtt_entries == 0) {
+               iounmap(intel_private.gtt);
+               iounmap(intel_private.registers);
+               return -ENOMEM;
+       }
 
        agp_bridge->gatt_table = NULL;
 
@@ -1274,6 +1315,16 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
        return addr | bridge->driver->masks[type].mask;
 }
 
+static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
+                                           dma_addr_t addr, int type)
+{
+       /* Shift high bits down */
+       addr |= (addr >> 28) & 0xff;
+
+       /* Type checking must be done elsewhere */
+       return addr | bridge->driver->masks[type].mask;
+}
+
 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
 {
        u16 snb_gmch_ctl;
@@ -1355,6 +1406,11 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 
        /* we have to call this as early as possible after the MMIO base address is known */
        intel_i830_init_gtt_entries();
+       if (intel_private.gtt_entries == 0) {
+               iounmap(intel_private.gtt);
+               iounmap(intel_private.registers);
+               return -ENOMEM;
+       }
 
        agp_bridge->gatt_table = NULL;
 
@@ -1422,7 +1478,7 @@ static const struct agp_bridge_driver intel_915_driver = {
        .size_type              = FIXED_APER_SIZE,
        .num_aperture_sizes     = 4,
        .needs_scratch_page     = true,
-       .configure              = intel_i915_configure,
+       .configure              = intel_i9xx_configure,
        .fetch_size             = intel_i9xx_fetch_size,
        .cleanup                = intel_i915_cleanup,
        .mask_memory            = intel_i810_mask_memory,
@@ -1455,7 +1511,7 @@ static const struct agp_bridge_driver intel_i965_driver = {
        .size_type              = FIXED_APER_SIZE,
        .num_aperture_sizes     = 4,
        .needs_scratch_page     = true,
-       .configure              = intel_i915_configure,
+       .configure              = intel_i9xx_configure,
        .fetch_size             = intel_i9xx_fetch_size,
        .cleanup                = intel_i915_cleanup,
        .mask_memory            = intel_i965_mask_memory,
@@ -1482,13 +1538,46 @@ static const struct agp_bridge_driver intel_i965_driver = {
 #endif
 };
 
+static const struct agp_bridge_driver intel_gen6_driver = {
+       .owner                  = THIS_MODULE,
+       .aperture_sizes         = intel_i830_sizes,
+       .size_type              = FIXED_APER_SIZE,
+       .num_aperture_sizes     = 4,
+       .needs_scratch_page     = true,
+       .configure              = intel_i9xx_configure,
+       .fetch_size             = intel_i9xx_fetch_size,
+       .cleanup                = intel_i915_cleanup,
+       .mask_memory            = intel_gen6_mask_memory,
+       .masks                  = intel_i810_masks,
+       .agp_enable             = intel_i810_agp_enable,
+       .cache_flush            = global_cache_flush,
+       .create_gatt_table      = intel_i965_create_gatt_table,
+       .free_gatt_table        = intel_i830_free_gatt_table,
+       .insert_memory          = intel_i915_insert_entries,
+       .remove_memory          = intel_i915_remove_entries,
+       .alloc_by_type          = intel_i830_alloc_by_type,
+       .free_by_type           = intel_i810_free_by_type,
+       .agp_alloc_page         = agp_generic_alloc_page,
+       .agp_alloc_pages        = agp_generic_alloc_pages,
+       .agp_destroy_page       = agp_generic_destroy_page,
+       .agp_destroy_pages      = agp_generic_destroy_pages,
+       .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
+       .chipset_flush          = intel_i915_chipset_flush,
+#ifdef USE_PCI_DMA_API
+       .agp_map_page           = intel_agp_map_page,
+       .agp_unmap_page         = intel_agp_unmap_page,
+       .agp_map_memory         = intel_agp_map_memory,
+       .agp_unmap_memory       = intel_agp_unmap_memory,
+#endif
+};
+
 static const struct agp_bridge_driver intel_g33_driver = {
        .owner                  = THIS_MODULE,
        .aperture_sizes         = intel_i830_sizes,
        .size_type              = FIXED_APER_SIZE,
        .num_aperture_sizes     = 4,
        .needs_scratch_page     = true,
-       .configure              = intel_i915_configure,
+       .configure              = intel_i9xx_configure,
        .fetch_size             = intel_i9xx_fetch_size,
        .cleanup                = intel_i915_cleanup,
        .mask_memory            = intel_i965_mask_memory,