EDAC, amd64: Read MC registers on AMD Fam17h

[mirror_ubuntu-bionic-kernel.git] / drivers / edac / amd64_edac.h

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index c08870479054c6277c3eefcd7bc776c687efd783..7381663936736f990aa2bd3c29fd5e22fc0faad3 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -118,6 +118,8 @@
 #define PCI_DEVICE_ID_AMD_16H_NB_F2    0x1532
 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
+#define PCI_DEVICE_ID_AMD_17H_DF_F0    0x1460
+#define PCI_DEVICE_ID_AMD_17H_DF_F6    0x1466
 
 /*
  * Function 1 - Address Map
@@ -248,6 +250,27 @@
 /* MSRs */
 #define MSR_MCGCTL_NBE                 BIT(4)
 
+/* F17h */
+
+/* F0: */
+#define DF_DHAR                                0x104
+
+/* UMC CH register offsets */
+#define UMCCH_BASE_ADDR                        0x0
+#define UMCCH_ADDR_MASK                        0x20
+#define UMCCH_DIMM_CFG                 0x80
+#define UMCCH_SDP_CTRL                 0x104
+#define UMCCH_ECC_CTRL                 0x14C
+#define UMCCH_UMC_CAP_HI               0xDF4
+
+/* UMC CH bitfields */
+#define UMC_ECC_CHIPKILL_CAP           BIT(31)
+#define UMC_ECC_ENABLED                        BIT(30)
+
+#define UMC_SDP_INIT                   BIT(31)
+
+#define NUM_UMCS                       2
+
 enum amd_families {
        K8_CPUS = 0,
        F10_CPUS,
@@ -256,6 +279,7 @@ enum amd_families {
        F15_M60H_CPUS,
        F16_CPUS,
        F16_M30H_CPUS,
+       F17_CPUS,
        NUM_FAMILIES,
 };
 
@@ -288,11 +312,17 @@ struct chip_select {
        u8 m_cnt;
 };
 
+struct amd64_umc {
+       u32 dimm_cfg;           /* DIMM Configuration reg */
+       u32 sdp_ctrl;           /* SDP Control reg */
+       u32 ecc_ctrl;           /* DRAM ECC Control reg */
+};
+
 struct amd64_pvt {
        struct low_ops *ops;
 
        /* pci_device handles which we utilize */
-       struct pci_dev *F1, *F2, *F3;
+       struct pci_dev *F0, *F1, *F2, *F3, *F6;
 
        u16 mc_node_id;         /* MC index of this MC node */
        u8 fam;                 /* CPU family */
@@ -335,6 +365,8 @@ struct amd64_pvt {
 
        /* cache the dram_type */
        enum mem_type dram_type;
+
+       struct amd64_umc *umc;  /* UMC registers */
 };
 
 enum err_codes {
@@ -354,6 +386,12 @@ struct err_info {
        u32 offset;
 };
 
+static inline u32 get_umc_base(u8 channel)
+{
+       /* ch0: 0x50000, ch1: 0x150000 */
+       return 0x50000 + (!!channel << 20);
+}
+
 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
 {
        u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
@@ -422,7 +460,7 @@ struct low_ops {
 
 struct amd64_family_type {
        const char *ctl_name;
-       u16 f1_id, f2_id;
+       u16 f0_id, f1_id, f2_id, f6_id;
        struct low_ops ops;
 };