drm/amdgpu: make pipeline sync be in same place v2

[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6a8129949333e9e395d8e5d5b78469c639438b27..e2cafbd690c0cc8a830845688b16f89cdf500b2b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -110,6 +110,7 @@ extern int amdgpu_pos_buf_per_se;
 extern int amdgpu_cntl_sb_buf_per_se;
 extern int amdgpu_param_buf_per_se;
 
+#define AMDGPU_DEFAULT_GTT_SIZE_MB             3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS         3000
 #define AMDGPU_MAX_USEC_TIMEOUT                        100000  /* 100 ms */
 #define AMDGPU_FENCE_JIFFIES_TIMEOUT           (HZ / 2)
@@ -553,7 +554,7 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
 int amdgpu_gart_init(struct amdgpu_device *adev);
 void amdgpu_gart_fini(struct amdgpu_device *adev);
-void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
+int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
                        int pages);
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                     int pages, struct page **pagelist,
@@ -906,6 +907,7 @@ struct amdgpu_mec {
 struct amdgpu_kiq {
        u64                     eop_gpu_addr;
        struct amdgpu_bo        *eop_obj;
+       struct mutex            ring_mutex;
        struct amdgpu_ring      ring;
        struct amdgpu_irq_src   irq;
 };
@@ -966,6 +968,8 @@ struct amdgpu_gfx_config {
        unsigned mc_arb_ramcfg;
        unsigned gb_addr_config;
        unsigned num_rbs;
+       unsigned gs_vgt_table_depth;
+       unsigned gs_prim_buffer_depth;
 
        uint32_t tile_mode_array[32];
        uint32_t macrotile_mode_array[16];
@@ -980,6 +984,7 @@ struct amdgpu_gfx_config {
 struct amdgpu_cu_info {
        uint32_t number; /* total active CU number */
        uint32_t ao_cu_mask;
+       uint32_t wave_front_size;
        uint32_t bitmap[4][4];
 };
 
@@ -1000,10 +1005,10 @@ struct amdgpu_ngg_buf {
 };
 
 enum {
-       PRIM = 0,
-       POS,
-       CNTL,
-       PARAM,
+       NGG_PRIM = 0,
+       NGG_POS,
+       NGG_CNTL,
+       NGG_PARAM,
        NGG_BUF_MAX
 };
 
@@ -1057,6 +1062,8 @@ struct amdgpu_gfx {
        uint32_t                        grbm_soft_reset;
        uint32_t                        srbm_soft_reset;
        bool                            in_reset;
+       /* s3/s4 mask */
+       bool                            in_suspend;
        /* NGG */
        struct amdgpu_ngg               ngg;
 };
@@ -1110,7 +1117,6 @@ struct amdgpu_cs_parser {
 #define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */
 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */
 #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */
-#define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in virtual memory context */
 
 struct amdgpu_job {
        struct amd_sched_job    base;
@@ -1118,6 +1124,7 @@ struct amdgpu_job {
        struct amdgpu_vm        *vm;
        struct amdgpu_ring      *ring;
        struct amdgpu_sync      sync;
+       struct amdgpu_sync      sched_sync;
        struct amdgpu_ib        *ibs;
        struct dma_fence        *fence; /* the hw fence */
        uint32_t                preamble_status;
@@ -1291,7 +1298,6 @@ struct amdgpu_smumgr {
  */
 struct amdgpu_allowed_register_entry {
        uint32_t reg_offset;
-       bool untouched;
        bool grbm_indexed;
 };
 
@@ -1704,9 +1710,6 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
 #define WREG32_FIELD_OFFSET(reg, offset, field, val)   \
        WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 
-#define WREG32_FIELD15(ip, idx, reg, field, val)       \
-       WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
-
 /*
  * BIOS helpers.
  */
@@ -1731,30 +1734,31 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *sr
        unsigned occupied, chunk1, chunk2;
        void *dst;
 
-       if (ring->count_dw < count_dw) {
+       if (unlikely(ring->count_dw < count_dw)) {
                DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
-       } else {
-               occupied = ring->wptr & ring->buf_mask;
-               dst = (void *)&ring->ring[occupied];
-               chunk1 = ring->buf_mask + 1 - occupied;
-               chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
-               chunk2 = count_dw - chunk1;
-               chunk1 <<= 2;
-               chunk2 <<= 2;
-
-               if (chunk1)
-                       memcpy(dst, src, chunk1);
-
-               if (chunk2) {
-                       src += chunk1;
-                       dst = (void *)ring->ring;
-                       memcpy(dst, src, chunk2);
-               }
-
-               ring->wptr += count_dw;
-               ring->wptr &= ring->ptr_mask;
-               ring->count_dw -= count_dw;
+               return;
+       }
+
+       occupied = ring->wptr & ring->buf_mask;
+       dst = (void *)&ring->ring[occupied];
+       chunk1 = ring->buf_mask + 1 - occupied;
+       chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
+       chunk2 = count_dw - chunk1;
+       chunk1 <<= 2;
+       chunk2 <<= 2;
+
+       if (chunk1)
+               memcpy(dst, src, chunk1);
+
+       if (chunk2) {
+               src += chunk1;
+               dst = (void *)ring->ring;
+               memcpy(dst, src, chunk2);
        }
+
+       ring->wptr += count_dw;
+       ring->wptr &= ring->ptr_mask;
+       ring->count_dw -= count_dw;
 }
 
 static inline struct amdgpu_sdma_instance *
@@ -1811,6 +1815,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
+#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
@@ -1910,10 +1915,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
-int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
-                                   int *max_error,
-                                   struct timeval *vblank_time,
-                                   unsigned flags);
 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
                             unsigned long arg);