ASoC: cs42xx8: fix the noise in the right dac channel with mono playback

[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / amd / amdgpu / cik.c

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 484710cfdf8243d563afe908c2b9c9884879f971..fd9c9588ef46335d7a154e664bce8275d62f3ae9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -32,6 +32,7 @@
 #include "amdgpu_vce.h"
 #include "cikd.h"
 #include "atom.h"
+#include "amd_pcie.h"
 
 #include "cik.h"
 #include "gmc_v7_0.h"
@@ -65,6 +66,7 @@
 #include "oss/oss_2_0_sh_mask.h"
 
 #include "amdgpu_amdkfd.h"
+#include "amdgpu_powerplay.h"
 
 /*
  * Indirect registers accessor
@@ -929,6 +931,37 @@ static bool cik_read_disabled_bios(struct amdgpu_device *adev)
        return r;
 }
 
+static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
+                                  u8 *bios, u32 length_bytes)
+{
+       u32 *dw_ptr;
+       unsigned long flags;
+       u32 i, length_dw;
+
+       if (bios == NULL)
+               return false;
+       if (length_bytes == 0)
+               return false;
+       /* APU vbios image is part of sbios image */
+       if (adev->flags & AMD_IS_APU)
+               return false;
+
+       dw_ptr = (u32 *)bios;
+       length_dw = ALIGN(length_bytes, 4) / 4;
+       /* take the smc lock since we are using the smc index */
+       spin_lock_irqsave(&adev->smc_idx_lock, flags);
+       /* set rom index to 0 */
+       WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
+       WREG32(mmSMC_IND_DATA_0, 0);
+       /* set index to data for continous read */
+       WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
+       for (i = 0; i < length_dw; i++)
+               dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
+       spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
+
+       return true;
+}
+
 static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
        {mmGRBM_STATUS, false},
        {mmGB_ADDR_CONFIG, false},
@@ -1563,8 +1596,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 {
        struct pci_dev *root = adev->pdev->bus->self;
        int bridge_pos, gpu_pos;
-       u32 speed_cntl, mask, current_data_rate;
-       int ret, i;
+       u32 speed_cntl, current_data_rate;
+       int i;
        u16 tmp16;
 
        if (pci_is_root_bus(adev->pdev->bus))
@@ -1576,23 +1609,20 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
        if (adev->flags & AMD_IS_APU)
                return;
 
-       ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-       if (ret != 0)
-               return;
-
-       if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+       if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+                                       CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
                return;
 
        speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
        current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
                PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
-       if (mask & DRM_PCIE_SPEED_80) {
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
                if (current_data_rate == 2) {
                        DRM_INFO("PCIE gen 3 link speeds already enabled\n");
                        return;
                }
                DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
-       } else if (mask & DRM_PCIE_SPEED_50) {
+       } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
                if (current_data_rate == 1) {
                        DRM_INFO("PCIE gen 2 link speeds already enabled\n");
                        return;
@@ -1608,7 +1638,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
        if (!gpu_pos)
                return;
 
-       if (mask & DRM_PCIE_SPEED_80) {
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
                /* re-try equalization if gen3 is not already enabled */
                if (current_data_rate != 2) {
                        u16 bridge_cfg, gpu_cfg;
@@ -1703,9 +1733,9 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 
        pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
        tmp16 &= ~0xf;
-       if (mask & DRM_PCIE_SPEED_80)
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
                tmp16 |= 3; /* gen3 */
-       else if (mask & DRM_PCIE_SPEED_50)
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
                tmp16 |= 2; /* gen2 */
        else
                tmp16 |= 1; /* gen1 */
@@ -1922,7 +1952,7 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
                .major = 7,
                .minor = 0,
                .rev = 0,
-               .funcs = &ci_dpm_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
@@ -1990,7 +2020,7 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
                .major = 7,
                .minor = 0,
                .rev = 0,
-               .funcs = &ci_dpm_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
@@ -2058,7 +2088,7 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
                .major = 7,
                .minor = 0,
                .rev = 0,
-               .funcs = &kv_dpm_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
@@ -2126,7 +2156,7 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
                .major = 7,
                .minor = 0,
                .rev = 0,
-               .funcs = &kv_dpm_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
@@ -2194,7 +2224,7 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
                .major = 7,
                .minor = 0,
                .rev = 0,
-               .funcs = &kv_dpm_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
@@ -2267,6 +2297,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 static const struct amdgpu_asic_funcs cik_asic_funcs =
 {
        .read_disabled_bios = &cik_read_disabled_bios,
+       .read_bios_from_rom = &cik_read_bios_from_rom,
        .read_register = &cik_read_register,
        .reset = &cik_asic_reset,
        .set_vga_state = &cik_vga_set_state,
@@ -2417,6 +2448,8 @@ static int cik_common_early_init(void *handle)
                return -EINVAL;
        }
 
+       amdgpu_get_pcie_info(adev);
+
        return 0;
 }