drm/amdgpu: unify MQD programming sequence for kfd and amdgpu v2

[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index fdab3994d447884e31f0870707aade6d41db1d92..06d106eab441727eed6cf9523142f9531729dcbd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3067,12 +3067,29 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
        /* set the vmid for the queue */
        mqd->cp_hqd_vmid = 0;
 
+       /* defaults */
+       mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
+       mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
+       mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
+       mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
+       mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
+       mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
+       mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
+       mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
+       mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
+       mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
+       mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
+       mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
+       mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+       mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
+       mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
+       mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
+
        /* activate the queue */
        mqd->cp_hqd_active = 1;
 }
 
-static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev,
-                              struct cik_mqd *mqd)
+int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
 {
        u32 tmp;
 
@@ -3096,6 +3113,23 @@ static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev,
        WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
        WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
 
+       WREG32(mmCP_HQD_IB_CONTROL, mqd->cp_hqd_ib_control);
+       WREG32(mmCP_HQD_IB_BASE_ADDR, mqd->cp_hqd_ib_base_addr_lo);
+       WREG32(mmCP_HQD_IB_BASE_ADDR_HI, mqd->cp_hqd_ib_base_addr_hi);
+       WREG32(mmCP_HQD_IB_RPTR, mqd->cp_hqd_ib_rptr);
+       WREG32(mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
+       WREG32(mmCP_HQD_SEMA_CMD, mqd->cp_hqd_sema_cmd);
+       WREG32(mmCP_HQD_MSG_TYPE, mqd->cp_hqd_msg_type);
+       WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, mqd->cp_hqd_atomic0_preop_lo);
+       WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, mqd->cp_hqd_atomic0_preop_hi);
+       WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, mqd->cp_hqd_atomic1_preop_lo);
+       WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, mqd->cp_hqd_atomic1_preop_hi);
+       WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
+       WREG32(mmCP_HQD_QUANTUM, mqd->cp_hqd_quantum);
+       WREG32(mmCP_HQD_PIPE_PRIORITY, mqd->cp_hqd_pipe_priority);
+       WREG32(mmCP_HQD_QUEUE_PRIORITY, mqd->cp_hqd_queue_priority);
+       WREG32(mmCP_HQD_IQ_RPTR, mqd->cp_hqd_iq_rptr);
+
        /* activate the HQD */
        WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);