drm/amdgpu: enable AGP aperture on gmc10.x (v2)

[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / mmhub_v2_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 2063700f0bc62edc9ccc78b44ccd4e88272b442b..57d5f8ffb764cc9257c44f7008c0522bb16df035 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -195,17 +195,17 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
        uint64_t value;
        uint32_t tmp;
 
-       /* Disable AGP. */
+       /* Program the AGP BAR */
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
-       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
-       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
+       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
        if (!amdgpu_sriov_vf(adev)) {
                /* Program the system aperture low logical page number. */
                WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                            adev->gmc.vram_start >> 18);
+                            min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
                WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                            adev->gmc.vram_end >> 18);
+                            max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
        }
 
        /* Set default page address. */
@@ -543,6 +543,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
                def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
                def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
                break;
@@ -576,6 +577,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
                if (def != data)
                        WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
                if (def1 != data1)
@@ -598,6 +600,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
                def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
                break;
        default:
@@ -614,6 +617,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
                switch (adev->asic_type) {
                case CHIP_SIENNA_CICHLID:
                case CHIP_NAVY_FLOUNDER:
+               case CHIP_DIMGREY_CAVEFISH:
                        WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
                        break;
                default:
@@ -635,6 +639,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
                mmhub_v2_0_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -657,6 +662,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
                data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
                data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
                break;