drm/amdgpu/atomfirmware: use proper index for querying vram type (v3)

[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / sdma_v5_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 3747c3f1f0cc81b4a55b8d2bcb8ba7f4488cb112..6cd5d4ad08173d3d9d8c040123235cc34d00974c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -21,8 +21,11 @@
  *
  */
 
+#include <linux/delay.h>
 #include <linux/firmware.h>
-#include <drm/drmP.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
 #include "amdgpu.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_trace.h"
@@ -42,6 +45,12 @@
 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
 
+MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
+MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
+
+MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
+MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
+
 #define SDMA1_REG_OFFSET 0x600
 #define SDMA0_HYP_DEC_REG_START 0x5880
 #define SDMA0_HYP_DEC_REG_END 0x5893
@@ -59,7 +68,7 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
@@ -71,7 +80,7 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
@@ -80,6 +89,18 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
+};
+
+static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+};
+
+static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 };
 
 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
@@ -111,6 +132,22 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_sdma_nv10,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
                break;
+       case CHIP_NAVI14:
+               soc15_program_register_sequence(adev,
+                                               golden_settings_sdma_5,
+                                               (const u32)ARRAY_SIZE(golden_settings_sdma_5));
+               soc15_program_register_sequence(adev,
+                                               golden_settings_sdma_nv14,
+                                               (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
+               break;
+       case CHIP_NAVI12:
+               soc15_program_register_sequence(adev,
+                                               golden_settings_sdma_5,
+                                               (const u32)ARRAY_SIZE(golden_settings_sdma_5));
+               soc15_program_register_sequence(adev,
+                                               golden_settings_sdma_nv12,
+                                               (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
+               break;
        default:
                break;
        }
@@ -143,6 +180,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
        case CHIP_NAVI10:
                chip_name = "navi10";
                break;
+       case CHIP_NAVI14:
+               chip_name = "navi14";
+               break;
+       case CHIP_NAVI12:
+               chip_name = "navi12";
+               break;
        default:
                BUG();
        }
@@ -363,7 +406,7 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
        u32 ref_and_mask = 0;
-       const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
+       const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 
        if (ring->me == 0)
                ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
@@ -373,8 +416,8 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
                          SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
                          SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
-       amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
-       amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
+       amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
+       amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
        amdgpu_ring_write(ring, ref_and_mask); /* reference */
        amdgpu_ring_write(ring, ref_and_mask); /* mask */
        amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
@@ -640,7 +683,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
                WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
                WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 
-               adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+               adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
                                                      ring->doorbell_index, 20);
 
                if (amdgpu_sriov_vf(adev))
@@ -861,7 +904,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
                if (amdgpu_emu_mode == 1)
                        msleep(1);
                else
-                       DRM_UDELAY(1);
+                       udelay(1);
        }
 
        if (i < adev->usec_timeout) {
@@ -1316,7 +1359,7 @@ static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
                if (ring->trail_seq ==
                    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        if (i >= adev->usec_timeout) {
@@ -1472,6 +1515,8 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                sdma_v5_0_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                sdma_v5_0_update_medium_grain_light_sleep(adev,
@@ -1532,7 +1577,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
-       .vmhub = AMDGPU_GFXHUB,
+       .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = sdma_v5_0_ring_get_rptr,
        .get_wptr = sdma_v5_0_ring_get_wptr,
        .set_wptr = sdma_v5_0_ring_set_wptr,
@@ -1583,7 +1628,8 @@ static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
 
 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-       adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+       adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
+                                       adev->sdma.num_instances;
        adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
        adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
 }