drm/amd/display: Rename more dc_surface stuff to plane_state

[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / calcs / dcn_calcs.c

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index c809ad3738e9edf32cf12205cc7cb0e1928729c1..404b39e7b44b7286ac583bcd4d9da10cb4aa01ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -233,16 +233,16 @@ static void pipe_ctx_to_e2e_pipe_params (
                struct _vcs_dpi_display_pipe_params_st *input)
 {
        input->src.is_hsplit = false;
-       if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface)
+       if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
                input->src.is_hsplit = true;
-       else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface)
+       else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
                input->src.is_hsplit = true;
 
-       input->src.dcc                 = pipe->surface->dcc.enable;
+       input->src.dcc                 = pipe->plane_state->dcc.enable;
        input->src.dcc_rate            = 1;
-       input->src.meta_pitch          = pipe->surface->dcc.grph.meta_pitch;
+       input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
        input->src.source_scan         = dm_horz;
-       input->src.sw_mode             = pipe->surface->tiling_info.gfx9.swizzle;
+       input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
 
        input->src.viewport_width      = pipe->scl_data.viewport.width;
        input->src.viewport_height     = pipe->scl_data.viewport.height;
@@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params (
        input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
        input->src.cur0_bpp            = 32;
 
-       switch (pipe->surface->tiling_info.gfx9.swizzle) {
+       switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
        /* for 4/8/16 high tiles */
        case DC_SW_LINEAR:
                input->src.is_display_sw = 1;
@@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params (
                break;
        }
 
-       switch (pipe->surface->rotation) {
+       switch (pipe->plane_state->rotation) {
        case ROTATION_ANGLE_0:
        case ROTATION_ANGLE_180:
                input->src.source_scan = dm_horz;
@@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params (
        }
 
        /* TODO: Fix pixel format mappings */
-       switch (pipe->surface->format) {
+       switch (pipe->plane_state->format) {
        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
                input->src.source_format = dm_420_8;
@@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu(
                        true,
                        true,
                        v->pte_enable == dcn_bw_yes,
-                       pipe->surface->flip_immediate);
+                       pipe->plane_state->flip_immediate);
 }
 
 static void dcn_dml_wm_override(
@@ -478,7 +478,7 @@ static void dcn_dml_wm_override(
        for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-               if (!pipe->stream || !pipe->surface)
+               if (!pipe->stream || !pipe->plane_state)
                        continue;
 
                input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
@@ -516,7 +516,7 @@ static void dcn_dml_wm_override(
        for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-               if (!pipe->stream || !pipe->surface)
+               if (!pipe->stream || !pipe->plane_state)
                        continue;
 
                dml_rq_dlg_get_dlg_reg(dml,
@@ -527,7 +527,7 @@ static void dcn_dml_wm_override(
                        true,
                        true,
                        v->pte_enable == dcn_bw_yes,
-                       pipe->surface->flip_immediate);
+                       pipe->plane_state->flip_immediate);
                in_idx++;
        }
        dm_free(input);
@@ -541,7 +541,7 @@ static void split_stream_across_pipes(
 {
        int pipe_idx = secondary_pipe->pipe_idx;
 
-       if (!primary_pipe->surface)
+       if (!primary_pipe->plane_state)
                return;
 
        *secondary_pipe = *primary_pipe;
@@ -843,7 +843,7 @@ bool dcn_validate_bandwidth(
                if (!pipe->stream)
                        continue;
                /* skip all but first of split pipes */
-               if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+               if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
                        continue;
 
                v->underscan_output[input_idx] = false; /* taken care of in recout already*/
@@ -856,9 +856,20 @@ bool dcn_validate_bandwidth(
                                - pipe->stream->timing.v_front_porch;
                v->vactive[input_idx] = pipe->stream->timing.v_addressable;
                v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
+               if (pipe->stream->sink->sink_signal ==  SIGNAL_TYPE_HDMI_TYPE_A) {
+                       switch (pipe->stream->timing.display_color_depth) {
+                       case COLOR_DEPTH_101010:
+                                       v->pixel_clock[input_idx]  = (v->pixel_clock[input_idx] * 30) / 24;
+                               break;
+                       case COLOR_DEPTH_121212:
+                               v->pixel_clock[input_idx]  = (v->pixel_clock[input_idx] * 36) / 24;
+                               break;
+                       default:
+                               break;
+                       }
+               }
 
-
-               if (!pipe->surface){
+               if (!pipe->plane_state) {
                        v->dcc_enable[input_idx] = dcn_bw_yes;
                        v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
                        v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
@@ -878,8 +889,8 @@ bool dcn_validate_bandwidth(
                        v->viewport_width[input_idx] = pipe->scl_data.viewport.width;
                        v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width;
                        v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height;
-                       if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) {
-                               if (pipe->surface->rotation % 2 == 0) {
+                       if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
+                               if (pipe->plane_state->rotation % 2 == 0) {
                                        int viewport_end = pipe->scl_data.viewport.width
                                                        + pipe->scl_data.viewport.x;
                                        int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width
@@ -908,17 +919,17 @@ bool dcn_validate_bandwidth(
                                                + pipe->bottom_pipe->scl_data.recout.width;
                        }
 
-                       v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no;
+                       v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
                        v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
-                                       pipe->surface->format);
+                                       pipe->plane_state->format);
                        v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
-                                       pipe->surface->tiling_info.gfx9.swizzle);
+                                       pipe->plane_state->tiling_info.gfx9.swizzle);
                        v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth);
                        v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps;
                        v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps;
                        v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c;
                        v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c;
-                       v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
+                       v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
                }
                if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
                        v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
@@ -985,7 +996,7 @@ bool dcn_validate_bandwidth(
                        if (!pipe->stream)
                                continue;
                        /* skip all but first of split pipes */
-                       if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+                       if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
                                continue;
 
                        pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
@@ -1013,7 +1024,7 @@ bool dcn_validate_bandwidth(
                        pipe->pipe_dlg_param.vblank_start = asic_blank_start;
                        pipe->pipe_dlg_param.vblank_end = asic_blank_end;
 
-                       if (pipe->surface) {
+                       if (pipe->plane_state) {
                                struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 
                                if (v->dpp_per_plane[input_idx] == 2 ||
@@ -1025,7 +1036,7 @@ bool dcn_validate_bandwidth(
                                         TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
                                         pipe->stream->timing.timing_3d_format ==
                                         TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
-                                       if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+                                       if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
                                                /* update previously split pipe */
                                                hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
                                                hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
@@ -1046,12 +1057,12 @@ bool dcn_validate_bandwidth(
                                        }
 
                                        dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe);
-                               } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+                               } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
                                        /* merge previously split pipe */
                                        pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
                                        if (hsplit_pipe->bottom_pipe)
                                                hsplit_pipe->bottom_pipe->top_pipe = pipe;
-                                       hsplit_pipe->surface = NULL;
+                                       hsplit_pipe->plane_state = NULL;
                                        hsplit_pipe->stream = NULL;
                                        hsplit_pipe->top_pipe = NULL;
                                        hsplit_pipe->bottom_pipe = NULL;