/* Defaults from spreadsheet rev#247 */
const struct dcn_soc_bounding_box dcn10_soc_defaults = {
- .sr_exit_time = 17, /*us*/ /*update based on HW Request for 118773*/
+ /* latencies */
+ .sr_exit_time = 17, /*us*/
.sr_enter_plus_exit_time = 19, /*us*/
.urgent_latency = 4, /*us*/
+ .dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
.percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
- .max_request_size = 256, /*bytes*/
- .dcfclkv_max0p9 = 600, /*MHz*/
- .dcfclkv_nom0p8 = 600, /*MHz*/
- .dcfclkv_mid0p72 = 300, /*MHz*/
- .dcfclkv_min0p65 = 300, /*MHz*/
- .max_dispclk_vmax0p9 = 1086, /*MHz*/
- .max_dispclk_vnom0p8 = 661, /*MHz*/
- .max_dispclk_vmid0p72 = 608, /*MHz*/
- .max_dispclk_vmin0p65 = 608, /*MHz*/
- .max_dppclk_vmax0p9 = 661, /*MHz*/
- .max_dppclk_vnom0p8 = 661, /*MHz*/
- .max_dppclk_vmid0p72 = 435, /*MHz*/
- .max_dppclk_vmin0p65 = 435, /*MHz*/
- .socclk = 208, /*MHz*/
+
+ /* below default clocks derived from STA target base on
+ * slow-slow corner + 10% margin with voltages aligned to FCLK.
+ *
+ * Use these value if fused value doesn't make sense as earlier
+ * part don't have correct value fused */
+ /* default DCF CLK DPM on RV*/
+ .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
+ .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
+ .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
+ .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
+
+ /* default DISP CLK voltage state on RV */
+ .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
+ .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
+ .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
+ .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
+
+ /* default DPP CLK voltage state on RV */
+ .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
+ .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
+ .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
+ .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
+
+ /* default PHY CLK voltage state on RV */
+ .phyclkv_max0p9 = 900, /*MHz*/
+ .phyclkv_nom0p8 = 847, /*MHz*/
+ .phyclkv_mid0p72 = 800, /*MHz*/
+ .phyclkv_min0p65 = 600, /*MHz*/
+
+ /* BW depend on FCLK, MCLK, # of channels */
+ /* dual channel BW */
.fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
- .fabric_and_dram_bandwidth_vnom0p8 = 34.1f, /*GB/s*/
- .fabric_and_dram_bandwidth_vmid0p72 = 29.8f, /*GB/s*/
+ .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
+ .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
.fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
- .phyclkv_max0p9 = 810, /*MHz*/
- .phyclkv_nom0p8 = 810, /*MHz*/
- .phyclkv_mid0p72 = 540, /*MHz*/
- .phyclkv_min0p65 = 540, /*MHz*/
+ /* single channel BW
+ .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
+ .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
+ .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
+ .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
+ */
+
+ .number_of_channels = 2,
+
+ .socclk = 208, /*MHz*/
.downspreading = 0.5f, /*%*/
.round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
.urgent_out_of_order_return_per_channel = 256, /*bytes*/
- .number_of_channels = 2,
.vmm_page_size = 4096, /*bytes*/
- .dram_clock_change_latency = 17, /*us*/
.return_bus_width = 64, /*bytes*/
+ .max_request_size = 256, /*bytes*/
+
+ /* Depends on user class (client vs embedded, workstation, etc) */
+ .percent_disp_bw_limit = 0.3f /*%*/
};
const struct dcn_ip_params dcn10_ip_defaults = {
struct _vcs_dpi_display_pipe_params_st *input)
{
input->src.is_hsplit = false;
- if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface)
+ if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
input->src.is_hsplit = true;
- else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface)
+ else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
input->src.is_hsplit = true;
- input->src.dcc = pipe->surface->public.dcc.enable;
+ input->src.dcc = pipe->plane_state->dcc.enable;
input->src.dcc_rate = 1;
- input->src.meta_pitch = pipe->surface->public.dcc.grph.meta_pitch;
+ input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch;
input->src.source_scan = dm_horz;
- input->src.sw_mode = pipe->surface->public.tiling_info.gfx9.swizzle;
+ input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
input->src.viewport_width = pipe->scl_data.viewport.width;
input->src.viewport_height = pipe->scl_data.viewport.height;
input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
input->src.cur0_bpp = 32;
- switch (pipe->surface->public.tiling_info.gfx9.swizzle) {
+ switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
/* for 4/8/16 high tiles */
case DC_SW_LINEAR:
input->src.is_display_sw = 1;
break;
case DC_SW_64KB_S:
case DC_SW_64KB_S_X:
+ case DC_SW_64KB_S_T:
input->src.is_display_sw = 0;
input->src.macro_tile_size = dm_64k_tile;
break;
break;
case DC_SW_64KB_D:
case DC_SW_64KB_D_X:
+ case DC_SW_64KB_D_T:
input->src.is_display_sw = 1;
input->src.macro_tile_size = dm_64k_tile;
break;
break;
}
- switch (pipe->surface->public.rotation) {
+ switch (pipe->plane_state->rotation) {
case ROTATION_ANGLE_0:
case ROTATION_ANGLE_180:
input->src.source_scan = dm_horz;
}
/* TODO: Fix pixel format mappings */
- switch (pipe->surface->public.format) {
+ switch (pipe->plane_state->format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
input->src.source_format = dm_420_8;
}
- input->dest.vactive = pipe->stream->public.timing.v_addressable;
+ input->dest.vactive = pipe->stream->timing.v_addressable;
input->dest.recout_width = pipe->scl_data.recout.width;
input->dest.recout_height = pipe->scl_data.recout.height;
input->dest.full_recout_width = pipe->scl_data.recout.width;
input->dest.full_recout_height = pipe->scl_data.recout.height;
- input->dest.htotal = pipe->stream->public.timing.h_total;
- input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch;
+ input->dest.htotal = pipe->stream->timing.h_total;
+ input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
input->dest.hblank_end = input->dest.hblank_start
- - pipe->stream->public.timing.h_addressable
- - pipe->stream->public.timing.h_border_left
- - pipe->stream->public.timing.h_border_right;
+ - pipe->stream->timing.h_addressable
+ - pipe->stream->timing.h_border_left
+ - pipe->stream->timing.h_border_right;
- input->dest.vtotal = pipe->stream->public.timing.v_total;
- input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch;
+ input->dest.vtotal = pipe->stream->timing.v_total;
+ input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
input->dest.vblank_end = input->dest.vblank_start
- - pipe->stream->public.timing.v_addressable
- - pipe->stream->public.timing.v_border_bottom
- - pipe->stream->public.timing.v_border_top;
-
- input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total
- - pipe->stream->public.timing.v_addressable
- - pipe->stream->public.timing.v_front_porch;
- input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0;
+ - pipe->stream->timing.v_addressable
+ - pipe->stream->timing.v_border_bottom
+ - pipe->stream->timing.v_border_top;
+
+ input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total
+ - pipe->stream->timing.v_addressable
+ - pipe->stream->timing.v_front_porch;
+ input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
true,
true,
v->pte_enable == dcn_bw_yes,
- pipe->surface->public.flip_immediate);
+ pipe->plane_state->flip_immediate);
}
static void dcn_dml_wm_override(
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream || !pipe->surface)
+ if (!pipe->stream || !pipe->plane_state)
continue;
input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
- context->watermarks.a.cstate_pstate.cstate_exit_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
a.cpstate.cstate_exit_us * 1000;
- context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
a.cpstate.cstate_enter_plus_exit_us * 1000;
- context->watermarks.a.cstate_pstate.pstate_change_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
a.cpstate.pstate_change_us * 1000;
- context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
- context->watermarks.a.urgent_ns = a.urgent * 1000;
- context->watermarks.b = context->watermarks.a;
- context->watermarks.c = context->watermarks.a;
- context->watermarks.d = context->watermarks.a;
+ context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
+ context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;
+ context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
+ context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
+ context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream || !pipe->surface)
+ if (!pipe->stream || !pipe->plane_state)
continue;
dml_rq_dlg_get_dlg_reg(dml,
true,
true,
v->pte_enable == dcn_bw_yes,
- pipe->surface->public.flip_immediate);
+ pipe->plane_state->flip_immediate);
in_idx++;
}
dm_free(input);
struct pipe_ctx *primary_pipe,
struct pipe_ctx *secondary_pipe)
{
- if (!primary_pipe->surface)
+ int pipe_idx = secondary_pipe->pipe_idx;
+
+ if (!primary_pipe->plane_state)
return;
- secondary_pipe->stream = primary_pipe->stream;
- secondary_pipe->tg = primary_pipe->tg;
+ *secondary_pipe = *primary_pipe;
+ secondary_pipe->pipe_idx = pipe_idx;
secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx];
secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx];
secondary_pipe->xfm = pool->transforms[secondary_pipe->pipe_idx];
- secondary_pipe->opp = pool->opps[secondary_pipe->pipe_idx];
if (primary_pipe->bottom_pipe) {
secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
}
primary_pipe->bottom_pipe = secondary_pipe;
secondary_pipe->top_pipe = primary_pipe;
- secondary_pipe->surface = primary_pipe->surface;
- secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param;
resource_build_scaling_params(primary_pipe);
resource_build_scaling_params(secondary_pipe);
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
- context->watermarks.b.cstate_pstate.cstate_exit_ns =
+ context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
v->stutter_exit_watermark * 1000;
- context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+ context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
v->stutter_enter_plus_exit_watermark * 1000;
- context->watermarks.b.cstate_pstate.pstate_change_ns =
+ context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
v->dram_clock_change_watermark * 1000;
- context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
- context->watermarks.b.urgent_ns = v->urgent_watermark * 1000;
+ context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
v->dcfclk = v->dcfclkv_nom0p8;
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
- context->watermarks.c.cstate_pstate.cstate_exit_ns =
+ context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
v->stutter_exit_watermark * 1000;
- context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+ context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
v->stutter_enter_plus_exit_watermark * 1000;
- context->watermarks.c.cstate_pstate.pstate_change_ns =
+ context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
v->dram_clock_change_watermark * 1000;
- context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
- context->watermarks.c.urgent_ns = v->urgent_watermark * 1000;
+ context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
}
if (v->voltage_level < 3) {
v->dcfclk = v->dcfclkv_max0p9;
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
- context->watermarks.d.cstate_pstate.cstate_exit_ns =
+ context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
v->stutter_exit_watermark * 1000;
- context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+ context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
v->stutter_enter_plus_exit_watermark * 1000;
- context->watermarks.d.cstate_pstate.pstate_change_ns =
+ context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
v->dram_clock_change_watermark * 1000;
- context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
- context->watermarks.d.urgent_ns = v->urgent_watermark * 1000;
+ context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
}
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
v->dcfclk = v->dcfclk_per_state[v->voltage_level];
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
- context->watermarks.a.cstate_pstate.cstate_exit_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
v->stutter_exit_watermark * 1000;
- context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
v->stutter_enter_plus_exit_watermark * 1000;
- context->watermarks.a.cstate_pstate.pstate_change_ns =
+ context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
v->dram_clock_change_watermark * 1000;
- context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
- context->watermarks.a.urgent_ns = v->urgent_watermark * 1000;
+ context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
if (v->voltage_level >= 2) {
- context->watermarks.b = context->watermarks.a;
- context->watermarks.c = context->watermarks.a;
+ context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
+ context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
}
if (v->voltage_level >= 3)
- context->watermarks.d = context->watermarks.a;
+ context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
}
-static void dcn_bw_apply_registry_override(struct core_dc *dc)
+static bool dcn_bw_apply_registry_override(struct core_dc *dc)
{
+ bool updated = false;
+
kernel_fpu_begin();
- if (dc->public.debug.sr_exit_time_ns)
+ if ((int)(dc->dcn_soc.sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns
+ && dc->public.debug.sr_exit_time_ns) {
+ updated = true;
dc->dcn_soc.sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0;
- if (dc->public.debug.sr_enter_plus_exit_time_ns)
+ }
+
+ if ((int)(dc->dcn_soc.sr_enter_plus_exit_time * 1000)
+ != dc->public.debug.sr_enter_plus_exit_time_ns
+ && dc->public.debug.sr_enter_plus_exit_time_ns) {
+ updated = true;
dc->dcn_soc.sr_enter_plus_exit_time =
dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0;
- if (dc->public.debug.urgent_latency_ns)
+ }
+
+ if ((int)(dc->dcn_soc.urgent_latency * 1000) != dc->public.debug.urgent_latency_ns
+ && dc->public.debug.urgent_latency_ns) {
+ updated = true;
dc->dcn_soc.urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0;
- if (dc->public.debug.percent_of_ideal_drambw)
+ }
+
+ if ((int)(dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency * 1000)
+ != dc->public.debug.percent_of_ideal_drambw
+ && dc->public.debug.percent_of_ideal_drambw) {
+ updated = true;
dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency =
dc->public.debug.percent_of_ideal_drambw;
- if (dc->public.debug.dram_clock_change_latency_ns)
+ }
+
+ if ((int)(dc->dcn_soc.dram_clock_change_latency * 1000)
+ != dc->public.debug.dram_clock_change_latency_ns
+ && dc->public.debug.dram_clock_change_latency_ns) {
+ updated = true;
dc->dcn_soc.dram_clock_change_latency =
dc->public.debug.dram_clock_change_latency_ns / 1000.0;
+ }
kernel_fpu_end();
+
+ return updated;
}
bool dcn_validate_bandwidth(
struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
int i, input_idx;
int vesa_sync_start, asic_blank_end, asic_blank_start;
+ bool bw_limit_pass;
+ float bw_limit;
- dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public));
+ if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public)))
+ dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public));
memset(v, 0, sizeof(*v));
kernel_fpu_begin();
v->phyclk_per_state[1] = v->phyclkv_mid0p72;
v->phyclk_per_state[0] = v->phyclkv_min0p65;
- if (dc->public.debug.use_max_voltage) {
- v->max_dppclk[1] = v->max_dppclk_vnom0p8;
- v->max_dppclk[0] = v->max_dppclk_vnom0p8;
+ if (dc->public.debug.disable_pipe_split) {
+ v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
if (v->voltage_override == dcn_bw_v_max0p9) {
if (!pipe->stream)
continue;
/* skip all but first of split pipes */
- if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+ if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
v->underscan_output[input_idx] = false; /* taken care of in recout already*/
v->interlace_output[input_idx] = false;
- v->htotal[input_idx] = pipe->stream->public.timing.h_total;
- v->vtotal[input_idx] = pipe->stream->public.timing.v_total;
- v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total
- - pipe->stream->public.timing.v_addressable
- - pipe->stream->public.timing.v_front_porch;
- v->vactive[input_idx] = pipe->stream->public.timing.v_addressable;
- v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f;
-
+ v->htotal[input_idx] = pipe->stream->timing.h_total;
+ v->vtotal[input_idx] = pipe->stream->timing.v_total;
+ v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
+ - pipe->stream->timing.v_addressable
+ - pipe->stream->timing.v_front_porch;
+ v->vactive[input_idx] = pipe->stream->timing.v_addressable;
+ v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
+ if (pipe->stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+ switch (pipe->stream->timing.display_color_depth) {
+ case COLOR_DEPTH_101010:
+ v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 30) / 24;
+ break;
+ case COLOR_DEPTH_121212:
+ v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 36) / 24;
+ break;
+ default:
+ break;
+ }
+ }
- if (!pipe->surface){
+ if (!pipe->plane_state) {
v->dcc_enable[input_idx] = dcn_bw_yes;
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
v->lb_bit_per_pixel[input_idx] = 30;
- v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable;
- v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable;
- v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable;
- v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable;
+ v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
+ v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
+ v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
+ v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
v->override_hta_ps[input_idx] = 1;
v->override_vta_ps[input_idx] = 1;
v->override_hta_pschroma[input_idx] = 1;
v->viewport_width[input_idx] = pipe->scl_data.viewport.width;
v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width;
v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height;
- if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) {
- if (pipe->surface->public.rotation % 2 == 0) {
+ if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
+ if (pipe->plane_state->rotation % 2 == 0) {
int viewport_end = pipe->scl_data.viewport.width
+ pipe->scl_data.viewport.x;
int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width
+ pipe->bottom_pipe->scl_data.recout.width;
}
- v->dcc_enable[input_idx] = pipe->surface->public.dcc.enable ? dcn_bw_yes : dcn_bw_no;
+ v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
- pipe->surface->public.format);
+ pipe->plane_state->format);
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
- pipe->surface->public.tiling_info.gfx9.swizzle);
+ pipe->plane_state->tiling_info.gfx9.swizzle);
v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth);
v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps;
v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps;
v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c;
v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c;
- v->source_scan[input_idx] = (pipe->surface->public.rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
+ v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
}
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
- v->output_format[input_idx] = dcn_bw_444;
- v->output[input_idx] = dcn_bw_dp;
+ v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
+ PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
+ v->output[input_idx] = pipe->stream->sink->sink_signal ==
+ SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
input_idx++;
}
scaler_settings_calculation(v);
mode_support_and_system_configuration(v);
+ if (v->voltage_level == 0 &&
+ (dc->public.debug.sr_exit_time_dpm0_ns
+ || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) {
+ struct core_dc *dc_core = DC_TO_CORE(&dc->public);
+
+ if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)
+ v->sr_enter_plus_exit_time =
+ dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
+ if (dc->public.debug.sr_exit_time_dpm0_ns)
+ v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f;
+ dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
+ dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
+ mode_support_and_system_configuration(v);
+ }
+
if (v->voltage_level != 5) {
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
display_pipe_configuration(v);
calc_wm_sets_and_perf_params(context, v);
- context->fclk_khz = (int)(bw_consumed * 1000000 /
+ context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
(ddr4_dram_factor_single_Channel * v->number_of_channels));
- context->dram_ccm_us = (int)(v->dram_clock_change_margin);
- context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
- context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
- context->dcfclk_khz = (int)(v->dcfclk * 1000);
- context->dispclk_khz = (int)(v->dispclk * 1000);
+ if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
+ context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
+ }
+
+ context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
+ context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
+ context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
+ context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
+ context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
if (dc->public.debug.max_disp_clk == true)
- context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
- context->dppclk_khz = (int)(v->dppclk * 1000);
- context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
+ context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
+ context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->stream)
continue;
/* skip all but first of split pipes */
- if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+ if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
- pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
- pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
- vesa_sync_start = pipe->stream->public.timing.v_addressable +
- pipe->stream->public.timing.v_border_bottom +
- pipe->stream->public.timing.v_front_porch;
+ pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
+ pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
+ vesa_sync_start = pipe->stream->timing.v_addressable +
+ pipe->stream->timing.v_border_bottom +
+ pipe->stream->timing.v_front_porch;
- asic_blank_end = (pipe->stream->public.timing.v_total -
+ asic_blank_end = (pipe->stream->timing.v_total -
vesa_sync_start -
- pipe->stream->public.timing.v_border_top)
- * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+ pipe->stream->timing.v_border_top)
+ * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
asic_blank_start = asic_blank_end +
- (pipe->stream->public.timing.v_border_top +
- pipe->stream->public.timing.v_addressable +
- pipe->stream->public.timing.v_border_bottom)
- * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+ (pipe->stream->timing.v_border_top +
+ pipe->stream->timing.v_addressable +
+ pipe->stream->timing.v_border_bottom)
+ * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
pipe->pipe_dlg_param.vblank_start = asic_blank_start;
pipe->pipe_dlg_param.vblank_end = asic_blank_end;
- if (pipe->surface) {
+ if (pipe->plane_state) {
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
if (v->dpp_per_plane[input_idx] == 2 ||
- (pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
- pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE)) {
- if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+ ((pipe->stream->view_format ==
+ VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+ pipe->stream->view_format ==
+ VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+ (pipe->stream->timing.timing_3d_format ==
+ TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+ pipe->stream->timing.timing_3d_format ==
+ TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
+ if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* update previously split pipe */
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
- hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
- hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
+ hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
+ hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
} else {
}
dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe);
- } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+ } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* merge previously split pipe */
- if (pipe->bottom_pipe->bottom_pipe)
- pipe->bottom_pipe->bottom_pipe->top_pipe = pipe;
- memset(pipe->bottom_pipe, 0, sizeof(*pipe->bottom_pipe));
- pipe->bottom_pipe = pipe->bottom_pipe->bottom_pipe;
+ pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
+ if (hsplit_pipe->bottom_pipe)
+ hsplit_pipe->bottom_pipe->top_pipe = pipe;
+ hsplit_pipe->plane_state = NULL;
+ hsplit_pipe->stream = NULL;
+ hsplit_pipe->top_pipe = NULL;
+ hsplit_pipe->bottom_pipe = NULL;
resource_build_scaling_params(pipe);
}
/* for now important to do this after pipe split for building e2e params */
&dc->dml, context, pool);
}
+ if (v->voltage_level == 0) {
+ struct core_dc *dc_core = DC_TO_CORE(&dc->public);
+
+ dc_core->dml.soc.sr_enter_plus_exit_time_us =
+ dc_core->dcn_soc.sr_enter_plus_exit_time;
+ dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time;
+ }
+
+ /*
+ * BW limit is set to prevent display from impacting other system functions
+ */
+
+ bw_limit = dc->dcn_soc.percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
+ bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
+
kernel_fpu_end();
- return v->voltage_level != 5;
+
+ if (bw_limit_pass && v->voltage_level != 5)
+ return true;
+ else
+ return false;
}
unsigned int dcn_find_normalized_clock_vdd_Level(
void dcn_bw_update_from_pplib(struct core_dc *dc)
{
struct dc_context *ctx = dc->ctx;
- struct dm_pp_clock_levels_with_latency clks = {0};
- struct dm_pp_clock_levels_with_voltage clks2 = {0};
+ struct dm_pp_clock_levels_with_voltage clks = {0};
kernel_fpu_begin();
- dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
- ASSERT(dc->dcn_soc.number_of_channels && dc->dcn_soc.number_of_channels < 3);
- if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
- dc->dcn_soc.number_of_channels = 2;
+
+ /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
if (dm_pp_get_clock_levels_by_type_with_voltage(
- ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clks2) &&
- clks2.num_levels >= 3) {
- dc->dcn_soc.max_dispclk_vmin0p65 = clks2.data[0].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dispclk_vmid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dispclk_vnom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dispclk_vmax0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
- } else
- BREAK_TO_DEBUGGER();
-/*
- if (dm_pp_get_clock_levels_by_type_with_latency(
- ctx, DM_PP_CLOCK_TYPE_MEMORY_CLK, &clks) &&
- clks.num_levels != 0) {
- //this is to get DRAM data_rate
- //FabricAndDRAMBandwidth = min(64*FCLK , Data rate * single_Channel_Width * number of channels);
- }*/
- if (dm_pp_get_clock_levels_by_type_with_latency(
ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) &&
clks.num_levels != 0) {
ASSERT(clks.num_levels >= 3);
- dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.number_of_channels *
- (clks.data[0].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0;
if (clks.num_levels > 2) {
dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
(clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
(clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
- if (dm_pp_get_clock_levels_by_type_with_latency(
+ if (dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) &&
clks.num_levels >= 3) {
dc->dcn_soc.dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0;
dc->dcn_soc.dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
} else
BREAK_TO_DEBUGGER();
- if (dm_pp_get_clock_levels_by_type_with_voltage(
- ctx, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, &clks2) &&
- clks2.num_levels >= 3) {
- dc->dcn_soc.phyclkv_min0p65 = clks2.data[0].clocks_in_khz / 1000.0;
- dc->dcn_soc.phyclkv_mid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
- dc->dcn_soc.phyclkv_nom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
- dc->dcn_soc.phyclkv_max0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
- } else
- BREAK_TO_DEBUGGER();
- if (dm_pp_get_clock_levels_by_type_with_latency(
- ctx, DM_PP_CLOCK_TYPE_DPPCLK, &clks) &&
- clks.num_levels >= 3) {
- dc->dcn_soc.max_dppclk_vmin0p65 = clks.data[0].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dppclk_vmid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dppclk_vnom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
- dc->dcn_soc.max_dppclk_vmax0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
- }
- if (dm_pp_get_clock_levels_by_type_with_latency(
- ctx, DM_PP_CLOCK_TYPE_SOCCLK, &clks) &&
- clks.num_levels >= 3) {
- dc->dcn_soc.socclk = clks.data[0].clocks_in_khz / 1000.0;
- } else
- BREAK_TO_DEBUGGER();
kernel_fpu_end();
}
{
struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0};
int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz,
- nom_dcfclk_khz, min_dcfclk_khz, socclk_khz;
+ nom_dcfclk_khz, mid_fclk_khz, min_dcfclk_khz, socclk_khz;
const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc.number_of_channels);
kernel_fpu_begin();
max_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
nom_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
- min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / factor;
+ mid_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor;
+ min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
max_dcfclk_khz = dc->dcn_soc.dcfclkv_max0p9 * 1000;
nom_dcfclk_khz = dc->dcn_soc.dcfclkv_nom0p8 * 1000;
min_dcfclk_khz = dc->dcn_soc.dcfclkv_min0p65 * 1000;
clk_ranges.num_wm_mcif_sets = 4;
clk_ranges.wm_dmif_clocks_ranges[0].wm_set_id = WM_SET_A;
clk_ranges.wm_dmif_clocks_ranges[0].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
- clk_ranges.wm_dmif_clocks_ranges[0].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
clk_ranges.wm_dmif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
- clk_ranges.wm_dmif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_max_mem_clk_in_khz = min_fclk_khz;
clk_ranges.wm_mcif_clocks_ranges[0].wm_set_id = WM_SET_A;
clk_ranges.wm_mcif_clocks_ranges[0].wm_min_socclk_clk_in_khz = socclk_khz;
clk_ranges.wm_mcif_clocks_ranges[0].wm_max_socclk_clk_in_khz = overdrive;
clk_ranges.wm_mcif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
- clk_ranges.wm_mcif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_max_mem_clk_in_khz = min_fclk_khz;
clk_ranges.wm_dmif_clocks_ranges[1].wm_set_id = WM_SET_B;
- clk_ranges.wm_dmif_clocks_ranges[1].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
- clk_ranges.wm_dmif_clocks_ranges[1].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
- clk_ranges.wm_dmif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
- clk_ranges.wm_dmif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_min_dcfclk_clk_in_khz = min_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_min_memg_clk_in_khz = mid_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_max_mem_clk_in_khz = mid_fclk_khz;
clk_ranges.wm_mcif_clocks_ranges[1].wm_set_id = WM_SET_B;
clk_ranges.wm_mcif_clocks_ranges[1].wm_min_socclk_clk_in_khz = socclk_khz;
clk_ranges.wm_mcif_clocks_ranges[1].wm_max_socclk_clk_in_khz = overdrive;
- clk_ranges.wm_mcif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
- clk_ranges.wm_mcif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_min_memg_clk_in_khz = mid_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_max_mem_clk_in_khz = mid_fclk_khz;
clk_ranges.wm_dmif_clocks_ranges[2].wm_set_id = WM_SET_C;
- clk_ranges.wm_dmif_clocks_ranges[2].wm_min_dcfclk_clk_in_khz = nom_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_min_dcfclk_clk_in_khz = min_fclk_khz;
clk_ranges.wm_dmif_clocks_ranges[2].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
clk_ranges.wm_dmif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
- clk_ranges.wm_dmif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_max_mem_clk_in_khz = nom_fclk_khz;
clk_ranges.wm_mcif_clocks_ranges[2].wm_set_id = WM_SET_C;
clk_ranges.wm_mcif_clocks_ranges[2].wm_min_socclk_clk_in_khz = socclk_khz;
clk_ranges.wm_mcif_clocks_ranges[2].wm_max_socclk_clk_in_khz = overdrive;
clk_ranges.wm_mcif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
- clk_ranges.wm_mcif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_max_mem_clk_in_khz = nom_fclk_khz;
clk_ranges.wm_dmif_clocks_ranges[3].wm_set_id = WM_SET_D;
- clk_ranges.wm_dmif_clocks_ranges[3].wm_min_dcfclk_clk_in_khz = max_dcfclk_khz + 1;
- clk_ranges.wm_dmif_clocks_ranges[3].wm_max_dcfclk_clk_in_khz = overdrive;
- clk_ranges.wm_dmif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
- clk_ranges.wm_dmif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_min_dcfclk_clk_in_khz = min_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_max_mem_clk_in_khz = max_fclk_khz;
clk_ranges.wm_mcif_clocks_ranges[3].wm_set_id = WM_SET_D;
clk_ranges.wm_mcif_clocks_ranges[3].wm_min_socclk_clk_in_khz = socclk_khz;
clk_ranges.wm_mcif_clocks_ranges[3].wm_max_socclk_clk_in_khz = overdrive;
- clk_ranges.wm_mcif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
- clk_ranges.wm_mcif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_max_mem_clk_in_khz = max_fclk_khz;
/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges);
void dcn_bw_sync_calcs_and_dml(struct core_dc *dc)
{
kernel_fpu_begin();
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "sr_exit_time: %d ns\n"
+ "sr_enter_plus_exit_time: %d ns\n"
+ "urgent_latency: %d ns\n"
+ "write_back_latency: %d ns\n"
+ "percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
+ "max_request_size: %d bytes\n"
+ "dcfclkv_max0p9: %d kHz\n"
+ "dcfclkv_nom0p8: %d kHz\n"
+ "dcfclkv_mid0p72: %d kHz\n"
+ "dcfclkv_min0p65: %d kHz\n"
+ "max_dispclk_vmax0p9: %d kHz\n"
+ "max_dispclk_vnom0p8: %d kHz\n"
+ "max_dispclk_vmid0p72: %d kHz\n"
+ "max_dispclk_vmin0p65: %d kHz\n"
+ "max_dppclk_vmax0p9: %d kHz\n"
+ "max_dppclk_vnom0p8: %d kHz\n"
+ "max_dppclk_vmid0p72: %d kHz\n"
+ "max_dppclk_vmin0p65: %d kHz\n"
+ "socclk: %d kHz\n"
+ "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
+ "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
+ "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
+ "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
+ "phyclkv_max0p9: %d kHz\n"
+ "phyclkv_nom0p8: %d kHz\n"
+ "phyclkv_mid0p72: %d kHz\n"
+ "phyclkv_min0p65: %d kHz\n"
+ "downspreading: %d %\n"
+ "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
+ "urgent_out_of_order_return_per_channel: %d Bytes\n"
+ "number_of_channels: %d\n"
+ "vmm_page_size: %d Bytes\n"
+ "dram_clock_change_latency: %d ns\n"
+ "return_bus_width: %d Bytes\n",
+ dc->dcn_soc.sr_exit_time * 1000,
+ dc->dcn_soc.sr_enter_plus_exit_time * 1000,
+ dc->dcn_soc.urgent_latency * 1000,
+ dc->dcn_soc.write_back_latency * 1000,
+ dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency,
+ dc->dcn_soc.max_request_size,
+ dc->dcn_soc.dcfclkv_max0p9 * 1000,
+ dc->dcn_soc.dcfclkv_nom0p8 * 1000,
+ dc->dcn_soc.dcfclkv_mid0p72 * 1000,
+ dc->dcn_soc.dcfclkv_min0p65 * 1000,
+ dc->dcn_soc.max_dispclk_vmax0p9 * 1000,
+ dc->dcn_soc.max_dispclk_vnom0p8 * 1000,
+ dc->dcn_soc.max_dispclk_vmid0p72 * 1000,
+ dc->dcn_soc.max_dispclk_vmin0p65 * 1000,
+ dc->dcn_soc.max_dppclk_vmax0p9 * 1000,
+ dc->dcn_soc.max_dppclk_vnom0p8 * 1000,
+ dc->dcn_soc.max_dppclk_vmid0p72 * 1000,
+ dc->dcn_soc.max_dppclk_vmin0p65 * 1000,
+ dc->dcn_soc.socclk * 1000,
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000,
+ dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000,
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 * 1000,
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000,
+ dc->dcn_soc.phyclkv_max0p9 * 1000,
+ dc->dcn_soc.phyclkv_nom0p8 * 1000,
+ dc->dcn_soc.phyclkv_mid0p72 * 1000,
+ dc->dcn_soc.phyclkv_min0p65 * 1000,
+ dc->dcn_soc.downspreading * 100,
+ dc->dcn_soc.round_trip_ping_latency_cycles,
+ dc->dcn_soc.urgent_out_of_order_return_per_channel,
+ dc->dcn_soc.number_of_channels,
+ dc->dcn_soc.vmm_page_size,
+ dc->dcn_soc.dram_clock_change_latency * 1000,
+ dc->dcn_soc.return_bus_width);
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ "rob_buffer_size_in_kbyte: %d\n"
+ "det_buffer_size_in_kbyte: %d\n"
+ "dpp_output_buffer_pixels: %d\n"
+ "opp_output_buffer_lines: %d\n"
+ "pixel_chunk_size_in_kbyte: %d\n"
+ "pte_enable: %d\n"
+ "pte_chunk_size: %d kbytes\n"
+ "meta_chunk_size: %d kbytes\n"
+ "writeback_chunk_size: %d kbytes\n"
+ "odm_capability: %d\n"
+ "dsc_capability: %d\n"
+ "line_buffer_size: %d bits\n"
+ "max_line_buffer_lines: %d\n"
+ "is_line_buffer_bpp_fixed: %d\n"
+ "line_buffer_fixed_bpp: %d\n"
+ "writeback_luma_buffer_size: %d kbytes\n"
+ "writeback_chroma_buffer_size: %d kbytes\n"
+ "max_num_dpp: %d\n"
+ "max_num_writeback: %d\n"
+ "max_dchub_topscl_throughput: %d pixels/dppclk\n"
+ "max_pscl_tolb_throughput: %d pixels/dppclk\n"
+ "max_lb_tovscl_throughput: %d pixels/dppclk\n"
+ "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
+ "max_hscl_ratio: %d\n"
+ "max_vscl_ratio: %d\n"
+ "max_hscl_taps: %d\n"
+ "max_vscl_taps: %d\n"
+ "pte_buffer_size_in_requests: %d\n"
+ "dispclk_ramping_margin: %d %\n"
+ "under_scan_factor: %d %\n"
+ "max_inter_dcn_tile_repeaters: %d\n"
+ "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
+ "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
+ "dcfclk_cstate_latency: %d\n",
+ dc->dcn_ip.rob_buffer_size_in_kbyte,
+ dc->dcn_ip.det_buffer_size_in_kbyte,
+ dc->dcn_ip.dpp_output_buffer_pixels,
+ dc->dcn_ip.opp_output_buffer_lines,
+ dc->dcn_ip.pixel_chunk_size_in_kbyte,
+ dc->dcn_ip.pte_enable,
+ dc->dcn_ip.pte_chunk_size,
+ dc->dcn_ip.meta_chunk_size,
+ dc->dcn_ip.writeback_chunk_size,
+ dc->dcn_ip.odm_capability,
+ dc->dcn_ip.dsc_capability,
+ dc->dcn_ip.line_buffer_size,
+ dc->dcn_ip.max_line_buffer_lines,
+ dc->dcn_ip.is_line_buffer_bpp_fixed,
+ dc->dcn_ip.line_buffer_fixed_bpp,
+ dc->dcn_ip.writeback_luma_buffer_size,
+ dc->dcn_ip.writeback_chroma_buffer_size,
+ dc->dcn_ip.max_num_dpp,
+ dc->dcn_ip.max_num_writeback,
+ dc->dcn_ip.max_dchub_topscl_throughput,
+ dc->dcn_ip.max_pscl_tolb_throughput,
+ dc->dcn_ip.max_lb_tovscl_throughput,
+ dc->dcn_ip.max_vscl_tohscl_throughput,
+ dc->dcn_ip.max_hscl_ratio,
+ dc->dcn_ip.max_vscl_ratio,
+ dc->dcn_ip.max_hscl_taps,
+ dc->dcn_ip.max_vscl_taps,
+ dc->dcn_ip.pte_buffer_size_in_requests,
+ dc->dcn_ip.dispclk_ramping_margin,
+ dc->dcn_ip.under_scan_factor * 100,
+ dc->dcn_ip.max_inter_dcn_tile_repeaters,
+ dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
+ dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed,
+ dc->dcn_ip.dcfclk_cstate_latency);
dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc.socclk;
dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc.socclk;
dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc.socclk;
projects / mirror_ubuntu-bionic-kernel.git / blobdiff