]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blobdiff - drivers/gpu/drm/amd/display/dc/dc_hw_types.h
drm/amd/display: Multi display synchronization logic
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / display / dc / dc_hw_types.h
index b785dd7b3a97382adb09dbad93e12825bf22cb4e..587c0bb3d4ac5193b6dd0f21e6005f6320b98425 100644 (file)
@@ -66,6 +66,7 @@ enum dc_plane_addr_type {
 
 struct dc_plane_address {
        enum dc_plane_addr_type type;
+       bool tmz_surface;
        union {
                struct{
                        PHYSICAL_ADDRESS_LOC addr;
@@ -99,15 +100,15 @@ struct dc_plane_address {
 };
 
 struct dc_size {
-       uint32_t width;
-       uint32_t height;
+       int width;
+       int height;
 };
 
 struct rect {
        int x;
        int y;
-       uint32_t width;
-       uint32_t height;
+       int width;
+       int height;
 };
 
 union plane_size {
@@ -123,7 +124,7 @@ union plane_size {
                 * In LINEAR_GENERAL mode, pitch
                 * is 32 pixel aligned.
                 */
-               uint32_t surface_pitch;
+               int surface_pitch;
        } grph;
 
        struct {
@@ -132,14 +133,14 @@ union plane_size {
                 * In LINEAR_GENERAL mode, pitch is
                 * 32 pixel aligned.
                 */
-               uint32_t luma_pitch;
+               int luma_pitch;
 
                struct rect chroma_size;
                /* Graphic surface pitch in pixels.
                 * In LINEAR_GENERAL mode, pitch is
                 * 32 pixel aligned.
                 */
-               uint32_t chroma_pitch;
+               int chroma_pitch;
        } video;
 };
 
@@ -148,15 +149,15 @@ struct dc_plane_dcc_param {
 
        union {
                struct {
-                       uint32_t meta_pitch;
+                       int meta_pitch;
                        bool independent_64b_blks;
                } grph;
 
                struct {
-                       uint32_t meta_pitch_l;
+                       int meta_pitch_l;
                        bool independent_64b_blks_l;
 
-                       uint32_t meta_pitch_c;
+                       int meta_pitch_c;
                        bool independent_64b_blks_c;
                } video;
        };
@@ -203,6 +204,8 @@ enum surface_pixel_format {
        /*grow 444 video here if necessary */
 };
 
+
+
 /* Pixel format */
 enum pixel_format {
        /*graph*/
@@ -214,15 +217,15 @@ enum pixel_format {
        PIXEL_FORMAT_ARGB2101010_XRBIAS,
        PIXEL_FORMAT_FP16,
        /*video*/
-       PIXEL_FORMAT_420BPP12,
-       PIXEL_FORMAT_420BPP15,
+       PIXEL_FORMAT_420BPP8,
+       PIXEL_FORMAT_420BPP10,
        /*end of pixel format definition*/
        PIXEL_FORMAT_INVALID,
 
        PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
        PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
-       PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
-       PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP15,
+       PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
+       PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
        PIXEL_FORMAT_UNKNOWN
 };
 
@@ -408,13 +411,29 @@ struct dc_cursor_mi_param {
 /* IPP related types */
 
 enum {
-       INPUT_LUT_ENTRIES = 256
+       GAMMA_RGB_256_ENTRIES = 256,
+       GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
+       GAMMA_MAX_ENTRIES = 1024
+};
+
+enum dc_gamma_type {
+       GAMMA_RGB_256 = 1,
+       GAMMA_RGB_FLOAT_1024 = 2
 };
 
 struct dc_gamma {
-       uint16_t red[INPUT_LUT_ENTRIES];
-       uint16_t green[INPUT_LUT_ENTRIES];
-       uint16_t blue[INPUT_LUT_ENTRIES];
+       struct kref refcount;
+       enum dc_gamma_type type;
+       unsigned int num_entries;
+
+       struct dc_gamma_entries {
+               struct fixed31_32 red[GAMMA_MAX_ENTRIES];
+               struct fixed31_32 green[GAMMA_MAX_ENTRIES];
+               struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
+       } entries;
+
+       /* private to DC core */
+       struct dc_context *ctx;
 };
 
 /* Used by both ipp amd opp functions*/
@@ -473,15 +492,53 @@ struct dc_cursor_attributes {
 enum dc_color_space {
        COLOR_SPACE_UNKNOWN,
        COLOR_SPACE_SRGB,
+       COLOR_SPACE_XR_RGB,
        COLOR_SPACE_SRGB_LIMITED,
+       COLOR_SPACE_MSREF_SCRGB,
        COLOR_SPACE_YCBCR601,
        COLOR_SPACE_YCBCR709,
+       COLOR_SPACE_XV_YCC_709,
+       COLOR_SPACE_XV_YCC_601,
        COLOR_SPACE_YCBCR601_LIMITED,
        COLOR_SPACE_YCBCR709_LIMITED,
        COLOR_SPACE_2020_RGB_FULLRANGE,
        COLOR_SPACE_2020_RGB_LIMITEDRANGE,
        COLOR_SPACE_2020_YCBCR,
        COLOR_SPACE_ADOBERGB,
+       COLOR_SPACE_DCIP3,
+       COLOR_SPACE_DISPLAYNATIVE,
+       COLOR_SPACE_DOLBYVISION,
+       COLOR_SPACE_APPCTRL,
+       COLOR_SPACE_CUSTOMPOINTS,
+};
+
+enum dc_dither_option {
+       DITHER_OPTION_DEFAULT,
+       DITHER_OPTION_DISABLE,
+       DITHER_OPTION_FM6,
+       DITHER_OPTION_FM8,
+       DITHER_OPTION_FM10,
+       DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
+       DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
+       DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
+       DITHER_OPTION_SPATIAL6,
+       DITHER_OPTION_SPATIAL8,
+       DITHER_OPTION_SPATIAL10,
+       DITHER_OPTION_TRUN6,
+       DITHER_OPTION_TRUN8,
+       DITHER_OPTION_TRUN10,
+       DITHER_OPTION_TRUN10_SPATIAL8,
+       DITHER_OPTION_TRUN10_SPATIAL6,
+       DITHER_OPTION_TRUN10_FM8,
+       DITHER_OPTION_TRUN10_FM6,
+       DITHER_OPTION_TRUN10_SPATIAL8_FM6,
+       DITHER_OPTION_SPATIAL10_FM8,
+       DITHER_OPTION_SPATIAL10_FM6,
+       DITHER_OPTION_TRUN8_SPATIAL6,
+       DITHER_OPTION_TRUN8_FM6,
+       DITHER_OPTION_SPATIAL8_FM6,
+       DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
+       DITHER_OPTION_INVALID
 };
 
 enum dc_quantization_range {
@@ -492,7 +549,7 @@ enum dc_quantization_range {
 
 /* XFM */
 
-/* used in  struct dc_surface */
+/* used in  struct dc_plane_state */
 struct scaling_taps {
        uint32_t v_taps;
        uint32_t h_taps;
@@ -522,27 +579,7 @@ enum dc_timing_standard {
        TIMING_STANDARD_MAX
 };
 
-enum dc_timing_3d_format {
-       TIMING_3D_FORMAT_NONE,
-       TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-       TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
-       TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
-       /* for active DP-HDMI dongle*/
-       TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
-       TIMING_3D_FORMAT_HW_FRAME_PACKING,
-       TIMING_3D_FORMAT_SW_FRAME_PACKING,
-       TIMING_3D_FORMAT_ROW_INTERLEAVE,
-       TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
-       TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
-       TIMING_3D_FORMAT_SIDE_BY_SIDE,
-       TIMING_3D_FORMAT_TOP_AND_BOTTOM,
-       TIMING_3D_FORMAT_SBS_SW_PACKED,
-       /* Side-by-side, packed by application/driver into 2D frame*/
-       TIMING_3D_FORMAT_TB_SW_PACKED,
-       /* Top-and-bottom, packed by application/driver into 2D frame*/
 
-       TIMING_3D_FORMAT_MAX,
-};
 
 enum dc_color_depth {
        COLOR_DEPTH_UNDEFINED,
@@ -606,12 +643,53 @@ struct dc_crtc_timing_flags {
        uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
        uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 
+       uint32_t FORCE_HDR :1;
+
        /* HDMI 2.0 - Support scrambling for TMDS character
         * rates less than or equal to 340Mcsc */
        uint32_t LTE_340MCSC_SCRAMBLE:1;
 
 };
 
+enum dc_timing_3d_format {
+       TIMING_3D_FORMAT_NONE,
+       TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
+       TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
+       TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
+       /* for active DP-HDMI dongle*/
+       TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
+       TIMING_3D_FORMAT_HW_FRAME_PACKING,
+       TIMING_3D_FORMAT_SW_FRAME_PACKING,
+       TIMING_3D_FORMAT_ROW_INTERLEAVE,
+       TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
+       TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
+       TIMING_3D_FORMAT_SIDE_BY_SIDE,
+       TIMING_3D_FORMAT_TOP_AND_BOTTOM,
+       TIMING_3D_FORMAT_SBS_SW_PACKED,
+       /* Side-by-side, packed by application/driver into 2D frame*/
+       TIMING_3D_FORMAT_TB_SW_PACKED,
+       /* Top-and-bottom, packed by application/driver into 2D frame*/
+
+       TIMING_3D_FORMAT_MAX,
+};
+
+enum trigger_delay {
+       TRIGGER_DELAY_NEXT_PIXEL = 0,
+       TRIGGER_DELAY_NEXT_LINE,
+};
+
+enum crtc_event {
+       CRTC_EVENT_VSYNC_RISING = 0,
+       CRTC_EVENT_VSYNC_FALLING
+};
+
+struct crtc_trigger_info {
+       bool enabled;
+       struct dc_stream_state *event_source;
+       enum crtc_event event;
+       enum trigger_delay delay;
+};
+
 struct dc_crtc_timing {
 
        uint32_t h_total;
@@ -641,12 +719,12 @@ struct dc_crtc_timing {
        struct dc_crtc_timing_flags flags;
 };
 
-struct _dlg_otg_param {
-       int vstartup_start;
-       int vupdate_offset;
-       int vupdate_width;
-       int vready_offset;
-       enum signal_type signal;
+#define MAX_TG_COLOR_VALUE 0x3FF
+struct tg_color {
+       /* Maximum 10 bits color value */
+       uint16_t color_r_cr;
+       uint16_t color_g_y;
+       uint16_t color_b_cb;
 };
 
 #endif /* DC_HW_TYPES_H */