#include "irq/dce110/irq_service_dce110.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
-#include "dce110/dce110_mem_input.h"
-#include "dce110/dce110_mem_input_v.h"
-#include "dce110/dce110_ipp.h"
+
+#include "dce/dce_mem_input.h"
+#include "dce/dce_ipp.h"
#include "dce/dce_transform.h"
-#include "dce110/dce110_opp.h"
+#include "dce/dce_opp.h"
+#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
}
};
-static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
- {
- .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- },
- {
- .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
- - mmDPG_WATERMARK_MASK_CONTROL),
- .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
- - mmPIPE0_DMIF_BUFFER_CONTROL),
- }
-};
-
-
-static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
-{
- .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
-},
-{
- .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
-},
-{
- .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
-},
-{
- .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
-},
-{
- .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
-},
-{
- .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
-}
-};
-
-
-
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
.reg_name = mm ## block ## id ## _ ## reg_name
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+#define ipp_regs(id)\
+[id] = {\
+ IPP_DCE100_REG_LIST_DCE_BASE(id)\
+}
+
+static const struct dce_ipp_registers ipp_regs[] = {
+ ipp_regs(0),
+ ipp_regs(1),
+ ipp_regs(2),
+ ipp_regs(3),
+ ipp_regs(4),
+ ipp_regs(5)
+};
+
+static const struct dce_ipp_shift ipp_shift = {
+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_ipp_mask ipp_mask = {
+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE100(id)\
#define link_regs(id)\
[id] = {\
- LE_DCE110_REG_LIST(id)\
+ LE_DCE100_REG_LIST(id)\
}
static const struct dce110_link_enc_registers link_enc_regs[] = {
SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
};
+#define opp_regs(id)\
+[id] = {\
+ OPP_DCE_100_REG_LIST(id),\
+}
+
+static const struct dce_opp_registers opp_regs[] = {
+ opp_regs(0),
+ opp_regs(1),
+ opp_regs(2),
+ opp_regs(3),
+ opp_regs(4),
+ opp_regs(5)
+};
+
+static const struct dce_opp_shift opp_shift = {
+ OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
+};
+
+static const struct dce_opp_mask opp_mask = {
+ OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
+};
+
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
-static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
-{
- .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT_CONTROL),
- .dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-},
-{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- .dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- .dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{
- .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- .dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- .dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- .dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
- .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-}
-};
-
static const struct bios_registers bios_regs = {
.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
};
static struct mem_input *dce100_mem_input_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_mem_input_reg_offsets *offset)
+ uint32_t inst)
{
- struct dce110_mem_input *mem_input110 =
- dm_alloc(sizeof(struct dce110_mem_input));
+ struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
- if (!mem_input110)
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
return NULL;
-
- if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
- struct mem_input *mi = &mem_input110->base;
-
- mi->regs = &mi_regs[inst];
- mi->shifts = &mi_shifts;
- mi->masks = &mi_masks;
- mi->wa.single_head_rdreq_dmif_limit = 2;
- return mi;
}
- BREAK_TO_DEBUGGER();
- dm_free(mem_input110);
- return NULL;
+ dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ dce_mi->wa.single_head_rdreq_dmif_limit = 2;
+ return &dce_mi->base;
}
static void dce100_transform_destroy(struct transform **xfm)
}
static struct input_pixel_processor *dce100_ipp_create(
- struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_ipp_reg_offsets *offsets)
+ struct dc_context *ctx, uint32_t inst)
{
- struct dce110_ipp *ipp =
- dm_alloc(sizeof(struct dce110_ipp));
+ struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
- if (!ipp)
+ if (!ipp) {
+ BREAK_TO_DEBUGGER();
return NULL;
+ }
- if (dce110_ipp_construct(ipp, ctx, inst, offsets))
- return &ipp->base;
-
- BREAK_TO_DEBUGGER();
- dm_free(ipp);
- return NULL;
+ dce_ipp_construct(ipp, ctx, inst,
+ &ipp_regs[inst], &ipp_shift, &ipp_mask);
+ return &ipp->base;
}
+static const struct encoder_feature_support link_enc_feature = {
+ .max_hdmi_deep_color = COLOR_DEPTH_121212,
+ .max_hdmi_pixel_clock = 300000,
+ .flags.bits.IS_HBR2_CAPABLE = true,
+ .flags.bits.IS_TPS3_CAPABLE = true,
+ .flags.bits.IS_YCBCR_CAPABLE = true
+};
+
struct link_encoder *dce100_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
if (dce110_link_encoder_construct(
enc110,
enc_init_data,
+ &link_enc_feature,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) {
- enc110->base.features.ycbcr420_supported = false;
- enc110->base.features.max_hdmi_pixel_clock = 300000;
return &enc110->base;
}
struct output_pixel_processor *dce100_opp_create(
struct dc_context *ctx,
- uint32_t inst,
- const struct dce110_opp_reg_offsets *offset)
+ uint32_t inst)
{
struct dce110_opp *opp =
dm_alloc(sizeof(struct dce110_opp));
return NULL;
if (dce110_opp_construct(opp,
- ctx, inst, offset))
+ ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
return &opp->base;
BREAK_TO_DEBUGGER();
return NULL;
}
-void dce100_opp_destroy(struct output_pixel_processor **opp)
-{
- struct dce110_opp *dce110_opp;
-
- if (!opp || !*opp)
- return;
-
- dce110_opp = FROM_DCE11_OPP(*opp);
-
- dm_free(dce110_opp->regamma.coeff128_dx);
- dm_free(dce110_opp->regamma.coeff128_oem);
- dm_free(dce110_opp->regamma.coeff128);
- dm_free(dce110_opp->regamma.axis_x_1025);
- dm_free(dce110_opp->regamma.axis_x_256);
- dm_free(dce110_opp->regamma.coordinates_x);
- dm_free(dce110_opp->regamma.rgb_regamma);
- dm_free(dce110_opp->regamma.rgb_resulted);
- dm_free(dce110_opp->regamma.rgb_oem);
- dm_free(dce110_opp->regamma.rgb_user);
- dm_free(dce110_opp);
-
- *opp = NULL;
-}
-
struct clock_source *dce100_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.opps[i] != NULL)
- dce100_opp_destroy(&pool->base.opps[i]);
+ dce110_opp_destroy(&pool->base.opps[i]);
if (pool->base.transforms[i] != NULL)
dce100_transform_destroy(&pool->base.transforms[i]);
if (pool->base.ipps[i] != NULL)
- dce110_ipp_destroy(&pool->base.ipps[i]);
+ dce_ipp_destroy(&pool->base.ipps[i]);
if (pool->base.mis[i] != NULL) {
- dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
+ dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
pool->base.mis[i] = NULL;
}
}
if (pool->base.display_clock != NULL)
- pool->base.display_clock->funcs->destroy(
- &pool->base.display_clock);
- pool->base.display_clock = NULL;
+ dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
}
-static enum dc_status validate_mapped_resource(
+static enum dc_status build_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
- uint8_t i, j, k;
-
- for (i = 0; i < context->target_count; i++) {
- struct core_target *target = context->targets[i];
+ uint8_t i, j;
- for (j = 0; j < target->public.stream_count; j++) {
- struct core_stream *stream =
- DC_STREAM_TO_CORE(target->public.streams[j]);
- struct core_link *link = stream->sink->link;
+ for (i = 0; i < context->stream_count; i++) {
+ struct dc_stream_state *stream = context->streams[i];
- if (resource_is_stream_unchanged(dc->current_context, stream))
- continue;
-
- for (k = 0; k < MAX_PIPES; k++) {
- struct pipe_ctx *pipe_ctx =
- &context->res_ctx.pipe_ctx[k];
-
- if (context->res_ctx.pipe_ctx[k].stream != stream)
- continue;
-
- if (!pipe_ctx->tg->funcs->validate_timing(
- pipe_ctx->tg, &stream->public.timing))
- return DC_FAIL_CONTROLLER_VALIDATE;
-
- status = dce110_resource_build_pipe_hw_param(pipe_ctx);
+ if (old_context && resource_is_stream_unchanged(old_context, stream))
+ continue;
- if (status != DC_OK)
- return status;
+ for (j = 0; j < MAX_PIPES; j++) {
+ struct pipe_ctx *pipe_ctx =
+ &context->res_ctx.pipe_ctx[j];
- if (!link->link_enc->funcs->validate_output_with_stream(
- link->link_enc,
- pipe_ctx))
- return DC_FAIL_ENC_VALIDATE;
+ if (context->res_ctx.pipe_ctx[j].stream != stream)
+ continue;
- /* TODO: validate audio ASIC caps, encoder */
- status = dc_link_validate_mode_timing(stream,
- link,
- &stream->public.timing);
+ status = dce110_resource_build_pipe_hw_param(pipe_ctx);
- if (status != DC_OK)
- return status;
+ if (status != DC_OK)
+ return status;
- resource_build_info_frame(pipe_ctx);
+ resource_build_info_frame(pipe_ctx);
- /* do not need to validate non root pipes */
- break;
- }
+ /* do not need to validate non root pipes */
+ break;
}
}
return DC_OK;
}
-enum dc_status dce100_validate_bandwidth(
+bool dce100_validate_bandwidth(
const struct core_dc *dc,
struct validate_context *context)
{
/* TODO implement when needed but for now hardcode max value*/
- context->bw_results.dispclk_khz = 681000;
+ context->bw.dce.dispclk_khz = 681000;
+ context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
- return DC_OK;
+ return true;
}
static bool dce100_validate_surface_sets(
int i;
for (i = 0; i < set_count; i++) {
- if (set[i].surface_count == 0)
+ if (set[i].plane_count == 0)
continue;
- if (set[i].surface_count > 1)
+ if (set[i].plane_count > 1)
return false;
- if (set[i].surfaces[0]->clip_rect.width
- != set[i].target->streams[0]->src.width
- || set[i].surfaces[0]->clip_rect.height
- != set[i].target->streams[0]->src.height)
- return false;
- if (set[i].surfaces[0]->format
+ if (set[i].plane_states[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
}
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
struct dc_context *dc_ctx = dc->ctx;
enum dc_status result = DC_ERROR_UNEXPECTED;
if (!dce100_validate_surface_sets(set, set_count))
return DC_FAIL_SURFACE_VALIDATE;
- context->res_ctx.pool = dc->res_pool;
-
for (i = 0; i < set_count; i++) {
- context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
- dc_target_retain(&context->targets[i]->public);
- context->target_count++;
+ context->streams[i] = set[i].stream;
+ dc_stream_retain(context->streams[i]);
+ context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, old_context);
- if (!resource_validate_attach_surfaces(
- set, set_count, dc->current_context, context)) {
- DC_ERROR("Failed to attach surface to target!\n");
+ if (!resource_validate_attach_surfaces(set, set_count,
+ old_context, context, dc->res_pool)) {
+ DC_ERROR("Failed to attach surface to stream!\n");
return DC_FAIL_ATTACH_SURFACES;
}
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = build_mapped_resource(dc, context, old_context);
if (result == DC_OK)
result = resource_build_scaling_params_for_context(dc, context);
if (result == DC_OK)
- result = dce100_validate_bandwidth(dc, context);
+ if (!dce100_validate_bandwidth(dc, context))
+ result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
enum dc_status dce100_validate_guaranteed(
const struct core_dc *dc,
- const struct dc_target *dc_target,
+ struct dc_stream_state *dc_stream,
struct validate_context *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
- context->res_ctx.pool = dc->res_pool;
-
- context->targets[0] = DC_TARGET_TO_CORE(dc_target);
- dc_target_retain(&context->targets[0]->public);
- context->target_count++;
+ context->streams[0] = dc_stream;
+ dc_stream_retain(context->streams[0]);
+ context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_clock_resources(dc, context);
+ result = resource_map_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = build_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
- validate_guaranteed_copy_target(
- context, dc->public.caps.max_targets);
+ validate_guaranteed_copy_streams(
+ context, dc->public.caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
- result = dce100_validate_bandwidth(dc, context);
+ if (!dce100_validate_bandwidth(dc, context))
+ result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
*pool = NULL;
}
+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state)
+{
+
+ if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ return DC_OK;
+
+ return DC_FAIL_SURFACE_VALIDATE;
+}
+
static const struct resource_funcs dce100_res_pool_funcs = {
.destroy = dce100_destroy_resource_pool,
.link_enc_create = dce100_link_encoder_create,
.validate_with_context = dce100_validate_with_context,
.validate_guaranteed = dce100_validate_guaranteed,
- .validate_bandwidth = dce100_validate_bandwidth
+ .validate_bandwidth = dce100_validate_bandwidth,
+ .validate_plane = dce100_validate_plane,
};
static bool construct(
{
unsigned int i;
struct dc_context *ctx = dc->ctx;
- struct firmware_info info;
+ struct dc_firmware_info info;
struct dc_bios *bp;
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
bp = ctx->dc_bios;
}
}
- pool->base.display_clock = dal_display_clock_dce110_create(ctx);
+ pool->base.display_clock = dce_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
- dce110_resource_convert_clock_state_pp_to_dc(
- static_clk_info.max_clocks_state);
+ static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
+ dc->public.caps.max_cursor_size = 128;
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
goto res_create_fail;
}
- pool->base.mis[i] = dce100_mem_input_create(ctx, i,
- &dce100_mi_reg_offsets[i]);
+ pool->base.mis[i] = dce100_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
goto res_create_fail;
}
- pool->base.ipps[i] = dce100_ipp_create(ctx, i,
- &dce100_ipp_reg_offsets[i]);
+ pool->base.ipps[i] = dce100_ipp_create(ctx, i);
if (pool->base.ipps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
goto res_create_fail;
}
- pool->base.opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
+ pool->base.opps[i] = dce100_opp_create(ctx, i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
}
}
+ dc->public.caps.max_planes = pool->base.pipe_count;
+
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
goto res_create_fail;
projects / mirror_ubuntu-bionic-kernel.git / blobdiff