drm/amd/display: rename struct mem_input to hubp for dcn

[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ee63155c18958e3fc4a6de46b3a8c136c69ddd8a..c34dbcd1fba4123b6c03c10bee166cf25763ad67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -172,10 +172,10 @@ static void dcn10_log_hw_state(struct dc *dc)
                        "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 
        for (i = 0; i < pool->pipe_count; i++) {
-               struct mem_input *mi = pool->mis[i];
+               struct hubp *hubp = pool->hubps[i];
                struct dcn_hubp_state s;
 
-               dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
+               hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 
                DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
                                "%xh \t %xh \t %xh \t "
@@ -803,7 +803,7 @@ static void power_on_plane(
 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 {
        struct dce_hwseq *hws = dc->hwseq;
-       struct mem_input *mi = dc->res_pool->mis[0];
+       struct hubp *hubp = dc->res_pool->hubps[0];
        int pwr_status = 0;
 
        REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status);
@@ -811,7 +811,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
        if (pwr_status == 2)
                return;
 
-       mi->funcs->set_blank(mi, true);
+       hubp->funcs->set_blank(hubp, true);
 
        REG_SET(DC_IP_REQUEST_CNTL, 0,
                        IP_REQUEST_EN, 1);
@@ -824,7 +824,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 {
        struct dce_hwseq *hws = dc->hwseq;
-       struct mem_input *mi = dc->res_pool->mis[0];
+       struct hubp *hubp = dc->res_pool->hubps[0];
 
        if (dc->debug.disable_stutter)
                return;
@@ -836,7 +836,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
        REG_SET(DC_IP_REQUEST_CNTL, 0,
                        IP_REQUEST_EN, 0);
 
-       mi->funcs->set_hubp_blank_en(mi, false);
+       hubp->funcs->set_hubp_blank_en(hubp, false);
 }
 
 static void bios_golden_init(struct dc *dc)
@@ -1070,7 +1070,7 @@ static void reset_back_end_for_pipe(
 static void plane_atomic_disconnect(struct dc *dc,
                int fe_idx)
 {
-       struct mem_input *mi = dc->res_pool->mis[fe_idx];
+       struct hubp *hubp = dc->res_pool->hubps[fe_idx];
        struct mpc *mpc = dc->res_pool->mpc;
        int opp_id, z_idx;
        int mpcc_id = -1;
@@ -1094,7 +1094,7 @@ static void plane_atomic_disconnect(struct dc *dc,
 
        if (dc->debug.sanity_checks)
                verify_allow_pstate_change_high(dc->hwseq);
-       mi->funcs->dcc_control(mi, false, false);
+       hubp->funcs->dcc_control(hubp, false, false);
        if (dc->debug.sanity_checks)
                verify_allow_pstate_change_high(dc->hwseq);
 
@@ -1108,20 +1108,20 @@ static void plane_atomic_disable(struct dc *dc,
                int fe_idx)
 {
        struct dce_hwseq *hws = dc->hwseq;
-       struct mem_input *mi = dc->res_pool->mis[fe_idx];
+       struct hubp *hubp = dc->res_pool->hubps[fe_idx];
        struct mpc *mpc = dc->res_pool->mpc;
-       int opp_id = mi->opp_id;
+       int opp_id = hubp->opp_id;
 
        if (opp_id == 0xf)
                return;
 
-       mpc->funcs->wait_for_idle(mpc, mi->mpcc_id);
-       dc->res_pool->opps[mi->opp_id]->mpcc_disconnect_pending[mi->mpcc_id] = false;
+       mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
+       dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
        /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
                        "[debug_mpo: atomic disable finished on mpcc %d]\n",
                        fe_idx);*/
 
-       mi->funcs->set_blank(mi, true);
+       hubp->funcs->set_blank(hubp, true);
 
        if (dc->debug.sanity_checks)
                verify_allow_pstate_change_high(dc->hwseq);
@@ -1171,7 +1171,7 @@ static void reset_front_end(
 {
        struct dce_hwseq *hws = dc->hwseq;
        struct timing_generator *tg;
-       int opp_id = dc->res_pool->mis[fe_idx]->opp_id;
+       int opp_id = dc->res_pool->hubps[fe_idx]->opp_id;
 
        /*Already reset*/
        if (opp_id == 0xf)
@@ -1353,8 +1353,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
        if (plane_state == NULL)
                return;
        addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
-       pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
-                       pipe_ctx->plane_res.mi,
+       pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
+                       pipe_ctx->plane_res.hubp,
                        &plane_state->address,
                        plane_state->flip_immediate);
        plane_state->status.requested_address = plane_state->address;
@@ -1759,8 +1759,8 @@ static void dcn10_pipe_control_lock(
        struct pipe_ctx *pipe,
        bool lock)
 {
-       struct mem_input *mi = NULL;
-       mi = dc->res_pool->mis[pipe->pipe_idx];
+       struct hubp *hubp = NULL;
+       hubp = dc->res_pool->hubps[pipe->pipe_idx];
        /* use TG master update lock to lock everything on the TG
         * therefore only top pipe need to lock
         */
@@ -2181,7 +2181,7 @@ static void dcn10_get_surface_visual_confirm_color(
        }
 }
 
-static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
+static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
                struct vm_system_aperture_param *apt,
                struct dce_hwseq *hws)
 {
@@ -2206,7 +2206,7 @@ static void mmhub_read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
 }
 
 /* Temporary read settings, future will get values from kmd directly */
-static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi,
+static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
                struct vm_context0_param *vm0,
                struct dce_hwseq *hws)
 {
@@ -2250,22 +2250,22 @@ static void mmhub_read_vm_context0_settings(struct dcn10_mem_input *mi,
        vm0->pte_base.quad_part -= fb_offset.quad_part;
 }
 
-static void dcn10_program_pte_vm(struct mem_input *mem_input,
+static void dcn10_program_pte_vm(struct hubp *hubp,
                enum surface_pixel_format format,
                union dc_tiling_info *tiling_info,
                enum dc_rotation_angle rotation,
                struct dce_hwseq *hws)
 {
-       struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+       struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
        struct vm_system_aperture_param apt = { {{ 0 } } };
        struct vm_context0_param vm0 = { { { 0 } } };
 
 
-       mmhub_read_vm_system_aperture_settings(mi, &apt, hws);
-       mmhub_read_vm_context0_settings(mi, &vm0, hws);
+       mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
+       mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
 
-       mem_input->funcs->mem_input_set_vm_system_aperture_settings(mem_input, &apt);
-       mem_input->funcs->mem_input_set_vm_context0_settings(mem_input, &vm0);
+       hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
+       hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
 }
 
 static void update_dchubp_dpp(
@@ -2274,7 +2274,7 @@ static void update_dchubp_dpp(
        struct dc_state *context)
 {
        struct dce_hwseq *hws = dc->hwseq;
-       struct mem_input *mi = pipe_ctx->plane_res.mi;
+       struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct transform *xfm = pipe_ctx->plane_res.xfm;
        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
        union plane_size size = plane_state->plane_size;
@@ -2299,8 +2299,8 @@ static void update_dchubp_dpp(
         */
        REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
 
-       mi->funcs->mem_input_setup(
-               mi,
+       hubp->funcs->hubp_setup(
+               hubp,
                &pipe_ctx->dlg_regs,
                &pipe_ctx->ttu_regs,
                &pipe_ctx->rq_regs,
@@ -2310,7 +2310,7 @@ static void update_dchubp_dpp(
 
        if (dc->config.gpu_vm_support)
                dcn10_program_pte_vm(
-                               pipe_ctx->plane_res.mi,
+                               pipe_ctx->plane_res.hubp,
                                plane_state->format,
                                &plane_state->tiling_info,
                                plane_state->rotation,
@@ -2321,7 +2321,7 @@ static void update_dchubp_dpp(
                        plane_state->format,
                        EXPANSION_MODE_ZERO);
 
-       mpcc_cfg.dpp_id = mi->inst;
+       mpcc_cfg.dpp_id = hubp->inst;
        mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
        mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree);
        for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
@@ -2340,15 +2340,15 @@ static void update_dchubp_dpp(
        mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
                        pipe_ctx->stream->output_color_space)
                                        && per_pixel_alpha;
-       mi->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
-       mi->opp_id = mpcc_cfg.opp_id;
+       hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
+       hubp->opp_id = mpcc_cfg.opp_id;
 
        pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
        pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
        /* scaler configuration */
        pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(
                        pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data);
-       mi->funcs->mem_program_viewport(mi,
+       hubp->funcs->mem_program_viewport(hubp,
                        &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
 
        /*gamut remap*/
@@ -2358,8 +2358,8 @@ static void update_dchubp_dpp(
                        pipe_ctx->stream->output_color_space,
                        pipe_ctx->stream->csc_color_matrix.matrix);
 
-       mi->funcs->mem_input_program_surface_config(
-               mi,
+       hubp->funcs->hubp_program_surface_config(
+               hubp,
                plane_state->format,
                &plane_state->tiling_info,
                &size,
@@ -2370,7 +2370,7 @@ static void update_dchubp_dpp(
        dc->hwss.update_plane_addr(dc, pipe_ctx);
 
        if (is_pipe_tree_visible(pipe_ctx))
-               mi->funcs->set_blank(mi, false);
+               hubp->funcs->set_blank(hubp, false);
 }
 
 
@@ -2550,7 +2550,7 @@ static void dcn10_apply_ctx_for_surface(
                 */
 
                if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
-                       if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
+                       if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
                                dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
                                /*
                                 * power down fe will unlock when calling reset, need
@@ -2577,7 +2577,7 @@ static void dcn10_apply_ctx_for_surface(
                                        &(old_pipe_ctx->stream_res.opp->mpc_tree),
                                        old_pipe_ctx->stream_res.opp->inst,
                                        old_pipe_ctx->pipe_idx);
-                       old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true;
+                       old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true;
 
                        /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
                                        "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
@@ -2861,7 +2861,7 @@ static void dcn10_wait_for_mpcc_disconnect(
                if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
                        res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
                        pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
-                       res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true);
+                       res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
                        /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
                                        "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
                                        i);*/
@@ -2892,11 +2892,11 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
                return;
 
        plane_state->status.is_flip_pending =
-                       pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
-                                       pipe_ctx->plane_res.mi);
+                       pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
+                                       pipe_ctx->plane_res.hubp);
 
-       plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
-       if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
+       plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
+       if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
                        tg->funcs->is_stereo_left_eye) {
                plane_state->status.is_right_eye =
                                !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);