#include "dcn10/dcn10_ipp.h"
#include "dcn10/dcn10_mpc.h"
#include "irq/dcn10/irq_service_dcn10.h"
-#include "dcn10/dcn10_transform.h"
+#include "dcn10/dcn10_dpp.h"
#include "dcn10/dcn10_timing_generator.h"
#include "dcn10/dcn10_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
-/* GC */
-#define GC_BASE_INNER(seg) \
- GC_BASE__INST0_SEG ## seg
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+ MMHUB_BASE__INST0_SEG ## seg
-#define GC_BASE(seg) \
- GC_BASE_INNER(seg)
+#define MMHUB_BASE(seg) \
+ MMHUB_BASE_INNER(seg)
-#define GC_SR(reg_name)\
- .reg_name = GC_BASE(mm ## reg_name ## _BASE_IDX) + \
+#define MMHUB_SR(reg_name)\
+ .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
/* macros to expend register list macro defined in HW object header file
* end *********************/
-static const struct dce_disp_clk_registers disp_clk_regs = {
- CLK_DCN10_REG_LIST()
-};
-
-static const struct dce_disp_clk_shift disp_clk_shift = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-};
-
-static const struct dce_disp_clk_mask disp_clk_mask = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-};
static const struct dce_dmcu_registers dmcu_regs = {
DMCU_DCN10_REG_LIST()
#define ipp_regs(id)\
[id] = {\
- IPP_DCN10_REG_LIST(id),\
+ IPP_REG_LIST_DCN10(id),\
}
static const struct dcn10_ipp_registers ipp_regs[] = {
};
static const struct dcn10_ipp_shift ipp_shift = {
- IPP_DCN10_MASK_SH_LIST(__SHIFT)
+ IPP_MASK_SH_LIST_DCN10(__SHIFT)
};
static const struct dcn10_ipp_mask ipp_mask = {
- IPP_DCN10_MASK_SH_LIST(_MASK),
+ IPP_MASK_SH_LIST_DCN10(_MASK),
};
#define opp_regs(id)\
[id] = {\
- OPP_DCN10_REG_LIST(id),\
+ OPP_REG_LIST_DCN10(id),\
}
static const struct dcn10_opp_registers opp_regs[] = {
};
static const struct dcn10_opp_shift opp_shift = {
- OPP_DCN10_MASK_SH_LIST(__SHIFT)
+ OPP_MASK_SH_LIST_DCN10(__SHIFT)
};
static const struct dcn10_opp_mask opp_mask = {
- OPP_DCN10_MASK_SH_LIST(_MASK),
+ OPP_MASK_SH_LIST_DCN10(_MASK),
};
#define tf_regs(id)\
[id] = {\
- TF_REG_LIST_DCN(id),\
+ TF_REG_LIST_DCN10(id),\
}
-static const struct dcn_transform_registers tf_regs[] = {
+static const struct dcn_dpp_registers tf_regs[] = {
tf_regs(0),
tf_regs(1),
tf_regs(2),
tf_regs(3),
};
-static const struct dcn_transform_shift tf_shift = {
- TF_REG_LIST_SH_MASK_DCN(__SHIFT)
+static const struct dcn_dpp_shift tf_shift = {
+ TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
};
-static const struct dcn_transform_mask tf_mask = {
- TF_REG_LIST_SH_MASK_DCN(_MASK),
+static const struct dcn_dpp_mask tf_mask = {
+ TF_REG_LIST_SH_MASK_DCN10(_MASK),
};
-
static const struct dcn_mpc_registers mpc_regs = {
- MPC_COMMON_REG_LIST_DCN1_0(0),
- MPC_COMMON_REG_LIST_DCN1_0(1),
- MPC_COMMON_REG_LIST_DCN1_0(2),
- MPC_COMMON_REG_LIST_DCN1_0(3),
+ MPC_COMMON_REG_LIST_DCN1_0(0),
+ MPC_COMMON_REG_LIST_DCN1_0(1),
+ MPC_COMMON_REG_LIST_DCN1_0(2),
+ MPC_COMMON_REG_LIST_DCN1_0(3)
};
static const struct dcn_mpc_shift mpc_shift = {
#define mi_regs(id)\
[id] = {\
- MI_DCN10_REG_LIST(id)\
+ MI_REG_LIST_DCN10(id)\
}
};
static const struct dcn_mi_shift mi_shift = {
- MI_DCN10_MASK_SH_LIST(__SHIFT)
+ MI_MASK_SH_LIST_DCN10(__SHIFT)
};
static const struct dcn_mi_mask mi_mask = {
- MI_DCN10_MASK_SH_LIST(_MASK)
+ MI_MASK_SH_LIST_DCN10(_MASK)
};
#define clk_src_regs(index, pllid)\
static const struct dc_debug debug_defaults_drv = {
.disable_dcc = false,
- .disable_dpp_power_gate = false,
- .disable_hubp_power_gate = false,
+ .sanity_checks = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
+ .clock_trace = true,
.disable_pplib_clock_request = true,
- .disable_pplib_wm_range = true,
+ .disable_pplib_wm_range = false,
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
.use_dml_wm = false,
- .use_max_voltage = true
+ .disable_pipe_split = true
#endif
};
static const struct dc_debug debug_defaults_diags = {
- .disable_dpp_power_gate = false,
- .disable_hubp_power_gate = false,
- .disable_clock_gate = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = true,
+ .clock_trace = true,
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.use_dml_wm = false,
- .use_max_voltage = false
+ .disable_pipe_split = false
#endif
};
-static void dcn10_transform_destroy(struct transform **xfm)
+static void dcn10_dpp_destroy(struct transform **xfm)
{
- dm_free(TO_DCN10_TRANSFORM(*xfm));
+ dm_free(TO_DCN10_DPP(*xfm));
*xfm = NULL;
}
-static struct transform *dcn10_transform_create(
+static struct transform *dcn10_dpp_create(
struct dc_context *ctx,
uint32_t inst)
{
- struct dcn10_transform *transform =
- dm_alloc(sizeof(struct dcn10_transform));
+ struct dcn10_dpp *dpp =
+ dm_alloc(sizeof(struct dcn10_dpp));
- if (!transform)
+ if (!dpp)
return NULL;
- if (dcn10_transform_construct(transform, ctx,
+ if (dcn10_dpp_construct(dpp, ctx, inst,
&tf_regs[inst], &tf_shift, &tf_mask))
- return &transform->base;
+ return &dpp->base;
BREAK_TO_DEBUGGER();
- dm_free(transform);
+ dm_free(dpp);
return NULL;
}
return &opp->base;
}
-static struct mpc *dcn10_mpc_create(
- struct dc_context *ctx)
+static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
{
- struct dcn10_mpc *mpc = dm_alloc(sizeof(struct dcn10_mpc));
+ struct dcn10_mpc *mpc10 = dm_alloc(sizeof(struct dcn10_mpc));
- if (!mpc)
+ if (!mpc10)
return NULL;
- mpc->base.ctx = ctx;
- mpc->mpc_regs = &mpc_regs;
- mpc->mpc_shift = &mpc_shift;
- mpc->mpc_mask = &mpc_mask;
-
- return &mpc->base;
-}
-
-static void dcn10_mpc_destroy(struct mpc **mpc_base)
-{
- if (*mpc_base)
- dm_free(TO_DCN10_MPC(*mpc_base));
+ dcn10_mpc_construct(mpc10, ctx,
+ &mpc_regs,
+ &mpc_shift,
+ &mpc_mask,
+ 4);
- *mpc_base = NULL;
+ return &mpc10->base;
}
static struct timing_generator *dcn10_timing_generator_create(
struct dc_context *ctx,
struct resource_straps *straps)
{
- /* TODO: Registers are missing */
- /*REG_GET_2(CC_DC_HDMI_STRAPS,
- HDMI_DISABLE, &straps->hdmi_disable,
- AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-
- REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/
+ generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
+ FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
}
static struct audio *create_audio(
}
}
+ if (pool->base.mpc != NULL) {
+ dm_free(TO_DCN10_MPC(pool->base.mpc));
+ pool->base.mpc = NULL;
+ }
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
if (pool->base.transforms[i] != NULL)
- dcn10_transform_destroy(&pool->base.transforms[i]);
+ dcn10_dpp_destroy(&pool->base.transforms[i]);
if (pool->base.ipps[i] != NULL)
pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
pool->base.dp_clock_source = NULL;
}
- if (pool->base.mpc != NULL)
- dcn10_mpc_destroy(&pool->base.mpc);
-
if (pool->base.abm != NULL)
dce_abm_destroy(&pool->base.abm);
const struct pipe_ctx *pipe_ctx,
struct pixel_clk_params *pixel_clk_params)
{
- const struct core_stream *stream = pipe_ctx->stream;
- pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
+ const struct dc_stream_state *stream = pipe_ctx->stream;
+ pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
pixel_clk_params->signal_type = pipe_ctx->stream->signal;
pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
LINK_RATE_REF_FREQ_IN_KHZ;
pixel_clk_params->flags.ENABLE_SS = 0;
pixel_clk_params->color_depth =
- stream->public.timing.display_color_depth;
+ stream->timing.display_color_depth;
pixel_clk_params->flags.DISPLAY_BLANKED = 1;
- pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding;
+ pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
- if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
pixel_clk_params->color_depth = COLOR_DEPTH_888;
- if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
pixel_clk_params->requested_pix_clk /= 2;
- if (stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING ||
- stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_SW_FRAME_PACKING ||
- stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA)
- pixel_clk_params->requested_pix_clk *= 2;
}
-static void build_clamping_params(struct core_stream *stream)
+static void build_clamping_params(struct dc_stream_state *stream)
{
stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
- stream->clamping.c_depth = stream->public.timing.display_color_depth;
- stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding;
+ stream->clamping.c_depth = stream->timing.display_color_depth;
+ stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
}
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
&pipe_ctx->pix_clk_params,
&pipe_ctx->pll_settings);
- pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding;
+ pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
return DC_OK;
}
-static enum dc_status validate_mapped_resource(
+static enum dc_status build_mapped_resource(
const struct core_dc *dc,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status status = DC_OK;
uint8_t i, j;
for (i = 0; i < context->stream_count; i++) {
- struct core_stream *stream = context->streams[i];
- struct core_link *link = stream->sink->link;
+ struct dc_stream_state *stream = context->streams[i];
- if (resource_is_stream_unchanged(dc->current_context, stream)) {
- if (stream != NULL && dc->current_context->streams[i] != NULL) {
+ if (old_context && resource_is_stream_unchanged(old_context, stream)) {
+ if (stream != NULL && old_context->streams[i] != NULL) {
/* todo: shouldn't have to copy missing parameter here */
resource_build_bit_depth_reduction_params(stream,
&stream->bit_depth_params);
stream->clamping.pixel_encoding =
- stream->public.timing.pixel_encoding;
+ stream->timing.pixel_encoding;
resource_build_bit_depth_reduction_params(stream,
&stream->bit_depth_params);
if (context->res_ctx.pipe_ctx[j].stream != stream)
continue;
-
- if (!pipe_ctx->tg->funcs->validate_timing(
- pipe_ctx->tg, &stream->public.timing))
- return DC_FAIL_CONTROLLER_VALIDATE;
-
status = build_pipe_hw_param(pipe_ctx);
if (status != DC_OK)
return status;
- if (!link->link_enc->funcs->validate_output_with_stream(
- link->link_enc, pipe_ctx))
- return DC_FAIL_ENC_VALIDATE;
-
- /* TODO: validate audio ASIC caps, encoder */
-
- status = dc_link_validate_mode_timing(
- stream, link, &stream->public.timing);
-
- if (status != DC_OK)
- return status;
-
-
/* do not need to validate non root pipes */
break;
}
const struct core_dc *dc,
const struct dc_validation_set set[],
int set_count,
- struct validate_context *context)
+ struct validate_context *context,
+ struct validate_context *old_context)
{
enum dc_status result = DC_OK;
int i;
return result;
for (i = 0; i < set_count; i++) {
- context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
- dc_stream_retain(&context->streams[i]->public);
+ context->streams[i] = set[i].stream;
+ dc_stream_retain(context->streams[i]);
context->stream_count++;
}
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, old_context);
if (result != DC_OK)
return result;
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, old_context);
if (result != DC_OK)
return result;
- result = validate_mapped_resource(dc, context);
+ result = build_mapped_resource(dc, context, old_context);
if (result != DC_OK)
return result;
if (!resource_validate_attach_surfaces(set, set_count,
- dc->current_context, context, dc->res_pool))
+ old_context, context, dc->res_pool))
return DC_FAIL_ATTACH_SURFACES;
result = resource_build_scaling_params_for_context(dc, context);
enum dc_status dcn10_validate_guaranteed(
const struct core_dc *dc,
- const struct dc_stream *dc_stream,
+ struct dc_stream_state *dc_stream,
struct validate_context *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
- context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
- dc_stream_retain(&context->streams[0]->public);
+ context->streams[0] = dc_stream;
+ dc_stream_retain(context->streams[0]);
context->stream_count++;
- result = resource_map_pool_resources(dc, context);
+ result = resource_map_pool_resources(dc, context, NULL);
if (result == DC_OK)
- result = resource_map_phy_clock_resources(dc, context);
+ result = resource_map_phy_clock_resources(dc, context, NULL);
if (result == DC_OK)
- result = validate_mapped_resource(dc, context);
+ result = build_mapped_resource(dc, context, NULL);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
struct validate_context *context,
const struct resource_pool *pool,
- struct core_stream *stream)
+ struct dc_stream_state *stream)
{
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
idle_pipe->stream = head_pipe->stream;
idle_pipe->tg = head_pipe->tg;
+ idle_pipe->opp = head_pipe->opp;
idle_pipe->mi = pool->mis[idle_pipe->pipe_idx];
idle_pipe->ipp = pool->ipps[idle_pipe->pipe_idx];
idle_pipe->xfm = pool->transforms[idle_pipe->pipe_idx];
- idle_pipe->opp = pool->opps[idle_pipe->pipe_idx];
return idle_pipe;
}
dc->public.caps.i2c_speed_in_khz = 100;
dc->public.caps.max_cursor_size = 256;
+ dc->public.caps.max_slave_planes = 1;
+
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->public.debug = debug_defaults_drv;
else
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
- pool->base.display_clock = dce120_disp_clk_create(ctx,
- &disp_clk_regs,
- &disp_clk_shift,
- &disp_clk_mask);
+ pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
dc->dcn_ip = dcn10_ip_defaults;
dc->dcn_soc = dcn10_soc_defaults;
+
+ dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
+ ASSERT(dc->dcn_soc.number_of_channels < 3);
+ if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
+ dc->dcn_soc.number_of_channels = 2;
+
+ if (dc->dcn_soc.number_of_channels == 1) {
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
+ }
+
if (!dc->public.debug.disable_pplib_clock_request)
dcn_bw_update_from_pplib(dc);
dcn_bw_sync_calcs_and_dml(dc);
#endif
}
- /* mem input -> ipp -> transform -> opp -> TG */
+ /* mem input -> ipp -> dpp -> opp -> TG */
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.mis[i] = dcn10_mem_input_create(ctx, i);
if (pool->base.mis[i] == NULL) {
goto ipp_create_fail;
}
- pool->base.transforms[i] = dcn10_transform_create(ctx, i);
+ pool->base.transforms[i] = dcn10_dpp_create(ctx, i);
if (pool->base.transforms[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
- "DC: failed to create transform!\n");
- goto transform_create_fail;
+ "DC: failed to create dpp!\n");
+ goto dpp_create_fail;
}
pool->base.opps[i] = dcn10_opp_create(ctx, i);
goto otg_create_fail;
}
}
-
pool->base.mpc = dcn10_mpc_create(ctx);
+ if (pool->base.mpc == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create mpc!\n");
+ goto mpc_create_fail;
+ }
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
goto res_create_fail;
dcn10_hw_sequencer_construct(dc);
- dc->public.caps.max_surfaces = pool->base.pipe_count;
+ dc->public.caps.max_planes = pool->base.pipe_count;
dc->public.cap_funcs = cap_funcs;
return true;
disp_clk_create_fail:
+mpc_create_fail:
otg_create_fail:
opp_create_fail:
-transform_create_fail:
+dpp_create_fail:
ipp_create_fail:
mi_create_fail:
irqs_create_fail:
projects / mirror_ubuntu-bionic-kernel.git / blobdiff