.regs_offset = 0x40,
.id = 0,
.type = ATMEL_HLCDC_BASE_LAYER,
- .nconfigs = 5,
+ .cfgs_offset = 0x2c,
.layout = {
.xstride = { 2 },
.default_color = 3,
.regs_offset = 0x40,
.id = 0,
.type = ATMEL_HLCDC_BASE_LAYER,
- .nconfigs = 5,
+ .cfgs_offset = 0x2c,
.layout = {
.xstride = { 2 },
.default_color = 3,
.regs_offset = 0x100,
.id = 1,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 10,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x280,
.id = 2,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 17,
+ .cfgs_offset = 0x4c,
.layout = {
.pos = 2,
.size = 3,
.chroma_key = 10,
.chroma_key_mask = 11,
.general_config = 12,
+ .scaler_config = 13,
.csc = 14,
},
},
.regs_offset = 0x340,
.id = 3,
.type = ATMEL_HLCDC_CURSOR_LAYER,
- .nconfigs = 10,
.max_width = 128,
.max_height = 128,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x40,
.id = 0,
.type = ATMEL_HLCDC_BASE_LAYER,
- .nconfigs = 7,
+ .cfgs_offset = 0x2c,
.layout = {
.xstride = { 2 },
.default_color = 3,
.regs_offset = 0x140,
.id = 1,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 10,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x240,
.id = 2,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 10,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x340,
.id = 3,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 42,
+ .cfgs_offset = 0x4c,
.layout = {
.pos = 2,
.size = 3,
.chroma_key = 10,
.chroma_key_mask = 11,
.general_config = 12,
+ .scaler_config = 13,
+ .phicoeffs = {
+ .x = 17,
+ .y = 33,
+ },
.csc = 14,
},
},
.regs_offset = 0x440,
.id = 4,
.type = ATMEL_HLCDC_CURSOR_LAYER,
- .nconfigs = 10,
.max_width = 128,
.max_height = 128,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.chroma_key = 7,
.chroma_key_mask = 8,
.general_config = 9,
+ .scaler_config = 13,
},
},
};
.regs_offset = 0x40,
.id = 0,
.type = ATMEL_HLCDC_BASE_LAYER,
- .nconfigs = 7,
+ .cfgs_offset = 0x2c,
.layout = {
.xstride = { 2 },
.default_color = 3,
.regs_offset = 0x140,
.id = 1,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 10,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x240,
.id = 2,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 10,
+ .cfgs_offset = 0x2c,
.layout = {
.pos = 2,
.size = 3,
.regs_offset = 0x340,
.id = 3,
.type = ATMEL_HLCDC_OVERLAY_LAYER,
- .nconfigs = 42,
+ .cfgs_offset = 0x4c,
.layout = {
.pos = 2,
.size = 3,
.chroma_key = 10,
.chroma_key_mask = 11,
.general_config = 12,
+ .scaler_config = 13,
+ .phicoeffs = {
+ .x = 17,
+ .y = 33,
+ },
.csc = 14,
},
},
return MODE_OK;
}
+static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
+{
+ if (!layer)
+ return;
+
+ if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
+ layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
+ layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
+ atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
+}
+
static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
{
struct drm_device *dev = data;
atmel_hlcdc_crtc_irq(dc->crtc);
for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
- struct atmel_hlcdc_layer *layer = dc->layers[i];
-
- if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
- continue;
-
- atmel_hlcdc_layer_irq(layer);
+ if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
+ atmel_hlcdc_layer_irq(dc->layers[i]);
}
return IRQ_HANDLED;
static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
{
struct atmel_hlcdc_dc *dc = dev->dev_private;
- struct atmel_hlcdc_planes *planes;
int ret;
- int i;
drm_mode_config_init(dev);
return ret;
}
- planes = atmel_hlcdc_create_planes(dev);
- if (IS_ERR(planes)) {
- dev_err(dev->dev, "failed to create planes\n");
- return PTR_ERR(planes);
+ ret = atmel_hlcdc_create_planes(dev);
+ if (ret) {
+ dev_err(dev->dev, "failed to create planes: %d\n", ret);
+ return ret;
}
- dc->planes = planes;
-
- dc->layers[planes->primary->layer.desc->id] =
- &planes->primary->layer;
-
- if (planes->cursor)
- dc->layers[planes->cursor->layer.desc->id] =
- &planes->cursor->layer;
-
- for (i = 0; i < planes->noverlays; i++)
- dc->layers[planes->overlays[i]->layer.desc->id] =
- &planes->overlays[i]->layer;
-
ret = atmel_hlcdc_crtc_create(dev);
if (ret) {
dev_err(dev->dev, "failed to create crtc\n");
regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
}
-static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
- unsigned int pipe)
-{
- struct atmel_hlcdc_dc *dc = dev->dev_private;
-
- /* Enable SOF (Start Of Frame) interrupt for vblank counting */
- regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
-
- return 0;
-}
-
-static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
- unsigned int pipe)
-{
- struct atmel_hlcdc_dc *dc = dev->dev_private;
-
- regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
-}
-
static const struct file_operations fops = {
.owner = THIS_MODULE,
.open = drm_open,
.irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
.irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
.irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
- .get_vblank_counter = drm_vblank_no_hw_counter,
- .enable_vblank = atmel_hlcdc_dc_enable_vblank,
- .disable_vblank = atmel_hlcdc_dc_disable_vblank,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,