Merge drm-next into drm-intel-next-queued (this time for real)

[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 92883a40bdd51f6f587a0f51851826f3896245a3..7bbec5546d12f1b7edac53a53f73615decc04129 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -71,9 +71,9 @@
 #include "i915_gem_fence_reg.h"
 #include "i915_gem_object.h"
 #include "i915_gem_gtt.h"
-#include "i915_gem_request.h"
 #include "i915_gem_timeline.h"
 
+#include "i915_request.h"
 #include "i915_vma.h"
 
 #include "intel_gvt.h"
@@ -1231,7 +1231,7 @@ struct i915_gpu_error {
         *
         * #I915_WEDGED - If reset fails and we can no longer use the GPU,
         * we set the #I915_WEDGED bit. Prior to command submission, e.g.
-        * i915_gem_request_alloc(), this bit is checked and the sequence
+        * i915_request_alloc(), this bit is checked and the sequence
         * aborted (with -EIO reported to userspace) if set.
         */
        unsigned long flags;
@@ -2788,9 +2788,10 @@ intel_info(const struct drm_i915_private *dev_priv)
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)    (IS_I830(dev_priv) || IS_I845G(dev_priv))
 
-/* WaRsDisableCoarsePowerGating:skl,bxt */
+/* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
-       (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
+       (IS_CANNONLAKE(dev_priv) || \
+        IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
@@ -3329,7 +3330,7 @@ i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
 
 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
 void i915_vma_move_to_active(struct i915_vma *vma,
-                            struct drm_i915_gem_request *req,
+                            struct i915_request *rq,
                             unsigned int flags);
 int i915_gem_dumb_create(struct drm_file *file_priv,
                         struct drm_device *dev,
@@ -3344,11 +3345,9 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
 
 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
 
-struct drm_i915_gem_request *
+struct i915_request *
 i915_gem_find_active_request(struct intel_engine_cs *engine);
 
-void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
-
 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
 {
        return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
@@ -3380,7 +3379,7 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
        return READ_ONCE(error->reset_engine_count[engine->id]);
 }
 
-struct drm_i915_gem_request *
+struct i915_request *
 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
 void i915_gem_reset(struct drm_i915_private *dev_priv);
@@ -3389,7 +3388,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
-                          struct drm_i915_gem_request *request);
+                          struct i915_request *request);
 
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
@@ -4008,9 +4007,9 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
 }
 
 static inline bool
-__i915_request_irq_complete(const struct drm_i915_gem_request *req)
+__i915_request_irq_complete(const struct i915_request *rq)
 {
-       struct intel_engine_cs *engine = req->engine;
+       struct intel_engine_cs *engine = rq->engine;
        u32 seqno;
 
        /* Note that the engine may have wrapped around the seqno, and
@@ -4019,7 +4018,7 @@ __i915_request_irq_complete(const struct drm_i915_gem_request *req)
         * this by kicking all the waiters before resetting the seqno
         * in hardware, and also signal the fence.
         */
-       if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
+       if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
                return true;
 
        /* The request was dequeued before we were awoken. We check after
@@ -4028,14 +4027,14 @@ __i915_request_irq_complete(const struct drm_i915_gem_request *req)
         * the request execution are sufficient to ensure that a check
         * after reading the value from hw matches this request.
         */
-       seqno = i915_gem_request_global_seqno(req);
+       seqno = i915_request_global_seqno(rq);
        if (!seqno)
                return false;
 
        /* Before we do the heavier coherent read of the seqno,
         * check the value (hopefully) in the CPU cacheline.
         */
-       if (__i915_gem_request_completed(req, seqno))
+       if (__i915_request_completed(rq, seqno))
                return true;
 
        /* Ensure our read of the seqno is coherent so that we
@@ -4084,7 +4083,7 @@ __i915_request_irq_complete(const struct drm_i915_gem_request *req)
                        wake_up_process(b->irq_wait->tsk);
                spin_unlock_irq(&b->irq_lock);
 
-               if (__i915_gem_request_completed(req, seqno))
+               if (__i915_request_completed(rq, seqno))
                        return true;
        }