drm/i915: fix VLV limits

[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ae7c3779baef4fdd0034dc1201ea51b0f6afffa9..bdbad762134c6d12076563c277043c5137a1b972 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -396,15 +396,15 @@ static const intel_limit_t intel_limits_vlv_dac = {
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p = { .min = 10, .max = 30 },
-       .p1 = { .min = 2, .max = 3 },
+       .p1 = { .min = 1, .max = 3 },
        .p2 = { .dot_limit = 270000,
                .p2_slow = 2, .p2_fast = 20 },
        .find_pll = intel_vlv_find_best_pll,
 };
 
 static const intel_limit_t intel_limits_vlv_hdmi = {
-       .dot = { .min = 20000, .max = 165000 },
-       .vco = { .min = 4000000, .max = 5994000},
+       .dot = { .min = 25000, .max = 270000 },
+       .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
        .m = { .min = 60, .max = 300 }, /* guess */
        .m1 = { .min = 2, .max = 3 },
@@ -424,7 +424,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p = { .min = 10, .max = 30 },
-       .p1 = { .min = 2, .max = 3 },
+       .p1 = { .min = 1, .max = 3 },
        .p2 = { .dot_limit = 270000,
                .p2_slow = 2, .p2_fast = 20 },
        .find_pll = intel_vlv_find_best_pll,
@@ -1097,14 +1097,14 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
                pch_dpll = I915_READ(PCH_DPLL_SEL);
                cur_state = pll->pll_reg == _PCH_DPLL_B;
                if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
-                         "PLL[%d] not attached to this transcoder %d: %08x\n",
-                         cur_state, crtc->pipe, pch_dpll)) {
+                         "PLL[%d] not attached to this transcoder %c: %08x\n",
+                         cur_state, pipe_name(crtc->pipe), pch_dpll)) {
                        cur_state = !!(val >> (4*crtc->pipe + 3));
                        WARN(cur_state != state,
-                            "PLL[%d] not %s on this transcoder %d: %08x\n",
+                            "PLL[%d] not %s on this transcoder %c: %08x\n",
                             pll->pll_reg == _PCH_DPLL_B,
                             state_string(state),
-                            crtc->pipe,
+                            pipe_name(crtc->pipe),
                             val);
                }
        }
@@ -1302,8 +1302,8 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
                reg = SPCNTR(pipe, i);
                val = I915_READ(reg);
                WARN((val & SP_ENABLE),
-                    "sprite %d assertion failure, should be off on pipe %c but is still active\n",
-                    pipe * 2 + i, pipe_name(pipe));
+                    "sprite %c assertion failure, should be off on pipe %c but is still active\n",
+                    sprite_name(pipe, i), pipe_name(pipe));
        }
 }
 
@@ -1733,7 +1733,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 
        I915_WRITE(reg, val | TRANS_ENABLE);
        if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
-               DRM_ERROR("failed to enable transcoder %d\n", pipe);
+               DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
 }
 
 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -1786,7 +1786,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
        I915_WRITE(reg, val);
        /* wait for PCH transcoder off, transcoder state */
        if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
-               DRM_ERROR("failed to disable transcoder %d\n", pipe);
+               DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
 
        if (!HAS_PCH_IBX(dev)) {
                /* Workaround: Clear the timing override chicken bit again. */
@@ -2101,7 +2101,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
        case 1:
                break;
        default:
-               DRM_ERROR("Can't update plane %d in SAREA\n", plane);
+               DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                return -EINVAL;
        }
 
@@ -2198,7 +2198,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
        case 2:
                break;
        default:
-               DRM_ERROR("Can't update plane %d in SAREA\n", plane);
+               DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                return -EINVAL;
        }
 
@@ -2389,9 +2389,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
        }
 
        if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
-               DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
-                               intel_crtc->plane,
-                               INTEL_INFO(dev)->num_pipes);
+               DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
+                         plane_name(intel_crtc->plane),
+                         INTEL_INFO(dev)->num_pipes);
                return -EINVAL;
        }
 
@@ -3299,7 +3299,7 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 found:
        intel_crtc->pch_pll = pll;
        pll->refcount++;
-       DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
+       DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
 prepare: /* separate function? */
        DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
 
@@ -3324,7 +3324,7 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
        udelay(500);
        if (wait_for(I915_READ(dslreg) != temp, 5)) {
                if (wait_for(I915_READ(dslreg) != temp, 5))
-                       DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
+                       DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
        }
 }
 
@@ -4723,7 +4723,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                        dspcntr |= DISPPLANE_SEL_PIPE_B;
        }
 
-       DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+       DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
        drm_mode_debug_printmodeline(mode);
 
        intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
@@ -5344,11 +5344,11 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
        struct intel_crtc *pipe_B_crtc =
                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
 
-       DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
-                     intel_crtc->pipe, intel_crtc->fdi_lanes);
+       DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
+                     pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
        if (intel_crtc->fdi_lanes > 4) {
-               DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
-                             intel_crtc->pipe, intel_crtc->fdi_lanes);
+               DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
+                             pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                /* Clamp lanes to avoid programming the hw with bogus values. */
                intel_crtc->fdi_lanes = 4;
 
@@ -5364,8 +5364,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
        case PIPE_B:
                if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
                    intel_crtc->fdi_lanes > 2) {
-                       DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
-                                     intel_crtc->pipe, intel_crtc->fdi_lanes);
+                       DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
+                                     pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                        /* Clamp lanes to avoid programming the hw with bogus values. */
                        intel_crtc->fdi_lanes = 2;
 
@@ -5381,8 +5381,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
        case PIPE_C:
                if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
                        if (intel_crtc->fdi_lanes > 2) {
-                               DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
-                                             intel_crtc->pipe, intel_crtc->fdi_lanes);
+                               DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
+                                             pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                                /* Clamp lanes to avoid programming the hw with bogus values. */
                                intel_crtc->fdi_lanes = 2;
 
@@ -5647,7 +5647,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
        dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
                                     has_reduced_clock ? &fp2 : NULL);
 
-       DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
+       DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
        drm_mode_debug_printmodeline(mode);
 
        /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
@@ -5656,8 +5656,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
                pll = intel_get_pch_pll(intel_crtc, dpll, fp);
                if (pll == NULL) {
-                       DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
-                                        pipe);
+                       DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+                                        pipe_name(pipe));
                        return -EINVAL;
                }
        } else
@@ -5821,7 +5821,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
        /* determine panel color depth */
        dither = intel_crtc->config.dither;
 
-       DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
+       DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
        drm_mode_debug_printmodeline(mode);
 
        if (intel_crtc->config.has_dp_encoder)
@@ -6109,7 +6109,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
                eldv |= IBX_ELD_VALIDB << 4;
                eldv |= IBX_ELD_VALIDB << 8;
        } else {
-               DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
+               DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
                eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
        }
 
@@ -9051,8 +9051,8 @@ void intel_modeset_init(struct drm_device *dev)
                for (j = 0; j < dev_priv->num_plane; j++) {
                        ret = intel_plane_init(dev, i, j);
                        if (ret)
-                               DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
-                                             i, j, ret);
+                               DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
+                                             pipe_name(i), sprite_name(i, j), ret);
                }
        }