Merge tag 'drm-misc-next-2020-06-19' of git://anongit.freedesktop.org/drm/drm-misc...

[mirror_ubuntu-kernels.git] / drivers / gpu / drm / msm / adreno / a6xx_gpu.c

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 34b85aaec7470dc46aad0eff2b81a7cc0fbcf34a..68314dcfce188836f4d74c48407da90e459f68aa 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -414,7 +414,17 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
                a6xx_set_hwcg(gpu, true);
 
        /* VBIF/GBIF start*/
-       gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
+       if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
+               gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
+               gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
+               gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
+               gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
+               gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
+               gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
+       } else {
+               gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
+       }
+
        if (adreno_is_a630(adreno_gpu))
                gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
 
@@ -429,25 +439,35 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
        gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
        gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
 
-       /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
-       gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
-               REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
+       if (!adreno_is_a650(adreno_gpu)) {
+               /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
+               gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
+                       REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
 
-       gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
-               REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
-               0x00100000 + adreno_gpu->gmem - 1);
+               gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
+                       REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
+                       0x00100000 + adreno_gpu->gmem - 1);
+       }
 
        gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
        gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
 
-       gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
+       if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
+               gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
+       else
+               gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
        gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
 
        /* Setting the mem pool size */
        gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
 
        /* Setting the primFifo thresholds default values */
-       gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
+       if (adreno_is_a650(adreno_gpu))
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
+       else if (adreno_is_a640(adreno_gpu))
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
+       else
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
 
        /* Set the AHB default slave response to "ERROR" */
        gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
@@ -471,6 +491,19 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
 
        gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
 
+       /* Set weights for bicubic filtering */
+       if (adreno_is_a650(adreno_gpu)) {
+               gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
+               gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
+                       0x3fe05ff4);
+               gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
+                       0x3fa0ebee);
+               gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
+                       0x3f5193ed);
+               gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
+                       0x3f0243f0);
+       }
+
        /* Protect registers from the CP */
        gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
 
@@ -508,6 +541,11 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
                        A6XX_PROTECT_RDONLY(0x980, 0x4));
        gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
 
+       if (adreno_is_a650(adreno_gpu)) {
+               gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
+                       (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
+       }
+
        /* Enable interrupts */
        gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
 
@@ -566,8 +604,10 @@ out:
         */
        a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
 
-       /* Take the GMU out of its special boot mode */
-       a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
+       if (a6xx_gpu->gmu.legacy) {
+               /* Take the GMU out of its special boot mode */
+               a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
+       }
 
        return ret;
 }
@@ -810,6 +850,11 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
        struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
        u64 busy_cycles, busy_time;
 
+
+       /* Only read the gpu busy if the hardware is already active */
+       if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
+               return 0;
+
        busy_cycles = gmu_read64(&a6xx_gpu->gmu,
                        REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
                        REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
@@ -819,6 +864,8 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
 
        gpu->devfreq.busy_cycles = busy_cycles;
 
+       pm_runtime_put(a6xx_gpu->gmu.dev);
+
        if (WARN_ON(busy_time > ~0LU))
                return ~0LU;
 
@@ -846,6 +893,7 @@ static const struct adreno_gpu_funcs funcs = {
 #if defined(CONFIG_DRM_MSM_GPU_STATE)
                .gpu_state_get = a6xx_gpu_state_get,
                .gpu_state_put = a6xx_gpu_state_put,
+               .create_address_space = adreno_iommu_create_address_space,
 #endif
        },
        .get_timestamp = a6xx_get_timestamp,