Merge branch '4.8/omapdrm-pll' (omapdrm PLL work)

[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / omapdrm / dss / hdmi_pll.c

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
index f1015e8b82675ffe21f420c375e2ef429b3d88a1..dc0212a9754eb2e9f9c3b09da8422b5951814228 100644 (file)
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
@@ -17,6 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/seq_file.h>
+#include <linux/pm_runtime.h>
 
 #include <video/omapdss.h>
 
@@ -39,71 +40,14 @@ void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
        DUMPPLL(PLLCTRL_CFG4);
 }
 
-void hdmi_pll_compute(struct hdmi_pll_data *pll,
-       unsigned long target_tmds, struct dss_pll_clock_info *pi)
-{
-       unsigned long fint, clkdco, clkout;
-       unsigned long target_bitclk, target_clkdco;
-       unsigned long min_dco;
-       unsigned n, m, mf, m2, sd;
-       unsigned long clkin;
-       const struct dss_pll_hw *hw = pll->pll.hw;
-
-       clkin = clk_get_rate(pll->pll.clkin);
-
-       DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
-
-       target_bitclk = target_tmds * 10;
-
-       /* Fint */
-       n = DIV_ROUND_UP(clkin, hw->fint_max);
-       fint = clkin / n;
-
-       /* adjust m2 so that the clkdco will be high enough */
-       min_dco = roundup(hw->clkdco_min, fint);
-       m2 = DIV_ROUND_UP(min_dco, target_bitclk);
-       if (m2 == 0)
-               m2 = 1;
-
-       target_clkdco = target_bitclk * m2;
-       m = target_clkdco / fint;
-
-       clkdco = fint * m;
-
-       /* adjust clkdco with fractional mf */
-       if (WARN_ON(target_clkdco - clkdco > fint))
-               mf = 0;
-       else
-               mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
-
-       if (mf > 0)
-               clkdco += (u32)div_u64((u64)mf * fint, 262144);
-
-       clkout = clkdco / m2;
-
-       /* sigma-delta */
-       sd = DIV_ROUND_UP(fint * m, 250000000);
-
-       DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
-               n, m, mf, m2, sd);
-       DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
-
-       pi->n = n;
-       pi->m = m;
-       pi->mf = mf;
-       pi->mX[0] = m2;
-       pi->sd = sd;
-
-       pi->fint = fint;
-       pi->clkdco = clkdco;
-       pi->clkout[0] = clkout;
-}
-
 static int hdmi_pll_enable(struct dss_pll *dsspll)
 {
        struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
        struct hdmi_wp_data *wp = pll->wp;
-       u16 r = 0;
+       int r;
+
+       r = pm_runtime_get_sync(&pll->pdev->dev);
+       WARN_ON(r < 0);
 
        dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
 
@@ -118,10 +62,14 @@ static void hdmi_pll_disable(struct dss_pll *dsspll)
 {
        struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
        struct hdmi_wp_data *wp = pll->wp;
+       int r;
 
        hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 
        dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
+
+       r = pm_runtime_put_sync(&pll->pdev->dev);
+       WARN_ON(r < 0 && r != -ENOSYS);
 }
 
 static const struct dss_pll_ops dsi_pll_ops = {
@@ -131,6 +79,8 @@ static const struct dss_pll_ops dsi_pll_ops = {
 };
 
 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
+       .type = DSS_PLL_TYPE_B,
+
        .n_max = 255,
        .m_min = 20,
        .m_max = 4095,
@@ -154,6 +104,8 @@ static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
 };
 
 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
+       .type = DSS_PLL_TYPE_B,
+
        .n_max = 255,
        .m_min = 20,
        .m_max = 2045,
@@ -225,6 +177,7 @@ int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
        int r;
        struct resource *res;
 
+       pll->pdev = pdev;
        pll->wp = wp;
 
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");