]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blobdiff - drivers/gpu/drm/radeon/radeon_state.c
tree-wide: fix assorted typos all over the place
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon_state.c
index 2882f40d5ec563d4ac5760314ca2a8b7b5da8282..067167cb39cafa8444b2358cde28d5bc9e96f167 100644 (file)
@@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
        } while (i < nbox);
 }
 
-static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
+void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
        struct drm_radeon_master_private *master_priv = master->driver_priv;
@@ -1950,7 +1950,7 @@ static void radeon_apply_surface_regs(int surf_index,
  * Note that refcount can be at most 2, since during a free refcount=3
  * might mean we have to allocate a new surface which might not always
  * be available.
- * For example : we allocate three contigous surfaces ABC. If B is
+ * For example : we allocate three contiguous surfaces ABC. If B is
  * freed, we suddenly need two surfaces to store A and C, which might
  * not always be available.
  */
@@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
        if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
                sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
-       radeon_cp_dispatch_swap(dev, file_priv->master);
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+               r600_cp_dispatch_swap(dev, file_priv);
+       else
+               radeon_cp_dispatch_swap(dev, file_priv->master);
        sarea_priv->ctx_owner = 0;
 
        COMMIT_RING();
@@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file
        RING_SPACE_TEST_WITH_RETURN(dev_priv);
        VB_AGE_TEST_WITH_RETURN(dev_priv);
 
-       ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+               ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
+       else
+               ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
 
        return ret;
 }
@@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
                radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
        }
 
-       if (indirect->discard)
+       if (indirect->discard) {
                radeon_cp_discard_buffer(dev, file_priv->master, buf);
+       }
 
        COMMIT_RING();
        return 0;
@@ -3027,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
                value = GET_SCRATCH(dev_priv, 2);
                break;
        case RADEON_PARAM_IRQ_NR:
-               value = drm_dev_to_irq(dev);
+               if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+                       value = 0;
+               else
+                       value = drm_dev_to_irq(dev);
                break;
        case RADEON_PARAM_GART_BASE:
                value = dev_priv->gart_vm_start;
@@ -3227,7 +3237,8 @@ struct drm_ioctl_desc radeon_ioctls[] = {
        DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
-       DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH)
+       DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
+       DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
 };
 
 int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);