Merge branches 'arm/exynos', 'arm/omap', 'arm/rockchip', 'arm/mediatek', 'arm/smmu...

[mirror_ubuntu-artful-kernel.git] / drivers / iommu / exynos-iommu.c

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index c01bfcdb238316c049ae0dd6b4bf2d43c6c61440..2395478dde7518cb7e74049765888fbef1c64510 100644 (file)
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -171,6 +171,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
 #define REG_V5_PT_BASE_PFN     0x00C
 #define REG_V5_MMU_FLUSH_ALL   0x010
 #define REG_V5_MMU_FLUSH_ENTRY 0x014
+#define REG_V5_MMU_FLUSH_RANGE 0x018
+#define REG_V5_MMU_FLUSH_START 0x020
+#define REG_V5_MMU_FLUSH_END   0x024
 #define REG_V5_INT_STATUS      0x060
 #define REG_V5_INT_CLEAR       0x064
 #define REG_V5_FAULT_AR_VA     0x070
@@ -319,14 +322,23 @@ static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 {
        unsigned int i;
 
-       for (i = 0; i < num_inv; i++) {
-               if (MMU_MAJ_VER(data->version) < 5)
+       if (MMU_MAJ_VER(data->version) < 5) {
+               for (i = 0; i < num_inv; i++) {
                        writel((iova & SPAGE_MASK) | 1,
                                     data->sfrbase + REG_MMU_FLUSH_ENTRY);
-               else
+                       iova += SPAGE_SIZE;
+               }
+       } else {
+               if (num_inv == 1) {
                        writel((iova & SPAGE_MASK) | 1,
                                     data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
-               iova += SPAGE_SIZE;
+               } else {
+                       writel((iova & SPAGE_MASK),
+                                    data->sfrbase + REG_V5_MMU_FLUSH_START);
+                       writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE,
+                                    data->sfrbase + REG_V5_MMU_FLUSH_END);
+                       writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE);
+               }
        }
 }
 
@@ -747,16 +759,8 @@ static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
                goto err_counter;
 
        /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
-       for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
-               domain->pgtable[i + 0] = ZERO_LV2LINK;
-               domain->pgtable[i + 1] = ZERO_LV2LINK;
-               domain->pgtable[i + 2] = ZERO_LV2LINK;
-               domain->pgtable[i + 3] = ZERO_LV2LINK;
-               domain->pgtable[i + 4] = ZERO_LV2LINK;
-               domain->pgtable[i + 5] = ZERO_LV2LINK;
-               domain->pgtable[i + 6] = ZERO_LV2LINK;
-               domain->pgtable[i + 7] = ZERO_LV2LINK;
-       }
+       for (i = 0; i < NUM_LV1ENTRIES; i++)
+               domain->pgtable[i] = ZERO_LV2LINK;
 
        handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
                                DMA_TO_DEVICE);