Merge branches 'for-4.11/upstream-fixes', 'for-4.12/accutouch', 'for-4.12/cp2112...

[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci-esdhc.h

diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index de132e28175342ea5869f1da1c003a0d16c2b6a7..ece8b37e51ddde167b44069e80bdfb5c3105fa19 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -24,30 +24,36 @@
                                SDHCI_QUIRK_PIO_NEEDS_DELAY | \
                                SDHCI_QUIRK_NO_HISPD_BIT)
 
-#define ESDHC_PROCTL           0x28
-
-#define ESDHC_SYSTEM_CONTROL   0x2c
-#define ESDHC_CLOCK_MASK       0x0000fff0
-#define ESDHC_PREDIV_SHIFT     8
-#define ESDHC_DIVIDER_SHIFT    4
-#define ESDHC_CLOCK_PEREN      0x00000004
-#define ESDHC_CLOCK_HCKEN      0x00000002
-#define ESDHC_CLOCK_IPGEN      0x00000001
-
 /* pltfm-specific */
 #define ESDHC_HOST_CONTROL_LE  0x20
 
 /*
- * P2020 interpretation of the SDHCI_HOST_CONTROL register
+ * eSDHC register definition
  */
-#define ESDHC_CTRL_4BITBUS          (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS          (0x2 << 1)
-#define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)
-
-/* OF-specific */
-#define ESDHC_DMA_SYSCTL       0x40c
-#define ESDHC_DMA_SNOOP                0x00000040
 
-#define ESDHC_HOST_CONTROL_RES 0x01
+/* Present State Register */
+#define ESDHC_PRSSTAT                  0x24
+#define ESDHC_CLOCK_STABLE             0x00000008
+
+/* Protocol Control Register */
+#define ESDHC_PROCTL                   0x28
+#define ESDHC_CTRL_4BITBUS             (0x1 << 1)
+#define ESDHC_CTRL_8BITBUS             (0x2 << 1)
+#define ESDHC_CTRL_BUSWIDTH_MASK       (0x3 << 1)
+#define ESDHC_HOST_CONTROL_RES         0x01
+
+/* System Control Register */
+#define ESDHC_SYSTEM_CONTROL           0x2c
+#define ESDHC_CLOCK_MASK               0x0000fff0
+#define ESDHC_PREDIV_SHIFT             8
+#define ESDHC_DIVIDER_SHIFT            4
+#define ESDHC_CLOCK_SDCLKEN            0x00000008
+#define ESDHC_CLOCK_PEREN              0x00000004
+#define ESDHC_CLOCK_HCKEN              0x00000002
+#define ESDHC_CLOCK_IPGEN              0x00000001
+
+/* Control Register for DMA transfer */
+#define ESDHC_DMA_SYSCTL               0x40c
+#define ESDHC_DMA_SNOOP                        0x00000040
 
 #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */