bnx2x: Add dual-media changes

[mirror_ubuntu-bionic-kernel.git] / drivers / net / bnx2x / bnx2x_reg.h

diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index a1f3bf0cd630d2de15be155830ca7f038de904f7..f0a69563b66a2a81544120c1c2ab9c4b5bf02f98 100644 (file)
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -4964,6 +4964,8 @@
 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN                 0x0001
 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR                0x0040
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1                    0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII                      0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK                       0x0002
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX                     0x0004
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK                 0x0018
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT                3
@@ -5135,18 +5137,22 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR  0x8005
 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF    0x8007
 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
-#define MDIO_PMA_REG_8727_MISC_CTRL            0x8309
 #define MDIO_PMA_REG_8727_TX_CTRL1             0xca02
 #define MDIO_PMA_REG_8727_TX_CTRL2             0xca05
 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL         0xc808
 #define MDIO_PMA_REG_8727_GPIO_CTRL            0xc80e
+#define MDIO_PMA_REG_8727_PCS_GP               0xc842
+
+#define MDIO_AN_REG_8727_MISC_CTRL             0x8309
 
 #define MDIO_PMA_REG_8073_CHIP_REV                     0xc801
 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS            0xc820
 #define MDIO_PMA_REG_8073_XAUI_WA                      0xc841
+#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL             0xcd08
 
 #define MDIO_PMA_REG_7101_RESET        0xc000
 #define MDIO_PMA_REG_7107_LED_CNTL     0xc007
+#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
 #define MDIO_PMA_REG_7101_VER1         0xc026
 #define MDIO_PMA_REG_7101_VER2         0xc027
 
@@ -5188,6 +5194,8 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_XS_8706_REG_BANK_RX3      0x80ec
 #define MDIO_XS_8706_REG_BANK_RXA      0x80fc
 
+#define MDIO_XS_REG_8073_RX_CTRL_PCIE  0x80FA
+
 #define MDIO_AN_DEVAD                  0x7
 /*ieee*/
 #define MDIO_AN_REG_CTRL               0x0000
@@ -5210,14 +5218,40 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_AN_REG_CL37_FC_LP         0xffe5
 
 #define MDIO_AN_REG_8073_2_5G          0x8329
+#define MDIO_AN_REG_8073_BAM           0x8350
 
+#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL     0x0020
 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL       0xffe0
+#define MDIO_AN_REG_8481_LEGACY_MII_STATUS     0xffe1
 #define MDIO_AN_REG_8481_LEGACY_AN_ADV         0xffe4
+#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION   0xffe6
 #define MDIO_AN_REG_8481_1000T_CTRL            0xffe9
 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW   0xfff5
 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS  0xfff7
+#define MDIO_AN_REG_8481_AUX_CTRL              0xfff8
 #define MDIO_AN_REG_8481_LEGACY_SHADOW         0xfffc
 
+/* BCM84823 only */
+#define MDIO_CTL_DEVAD                 0x1e
+#define MDIO_CTL_REG_84823_MEDIA               0x401a
+#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK              0x0018
+       /* These pins configure the BCM84823 interface to MAC after reset. */
+#define MDIO_CTL_REG_84823_CTRL_MAC_XFI                        0x0008
+#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M            0x0010
+       /* These pins configure the BCM84823 interface to Line after reset. */
+#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK             0x0060
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L           0x0020
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI              0x0040
+       /* When this pin is active high during reset, 10GBASE-T core is power
+        * down, When it is active low the 10GBASE-T is power up
+        */
+#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN      0x0080
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK         0x0100
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER       0x0000
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER                0x0100
+#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G                      0x1000
+
+
 #define IGU_FUNC_BASE                  0x0400
 
 #define IGU_ADDR_MSIX                  0x0000