r8169: sync existing 8168 device hardware start sequences with vendor driver

[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c

diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 8086bacabcf318e005a06c501405c1e1a48b2eea..f0f842d7b941793a2e2a0786b77c407f14a39b09 100644 (file)
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1387,7 +1387,7 @@ static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
 {
        struct phy_reg phy_reg_init[] = {
                { 0x1f, 0x0001 },
@@ -1416,7 +1416,7 @@ static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
        mdio_write(ioaddr, 0x1f, 0x0000);
 }
 
-static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
 {
        struct phy_reg phy_reg_init[] = {
                { 0x1f, 0x0001 },
@@ -1495,10 +1495,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
                rtl8168cp_hw_phy_config(ioaddr);
                break;
        case RTL_GIGA_MAC_VER_19:
-               rtl8168c_hw_phy_config(ioaddr);
+               rtl8168c_1_hw_phy_config(ioaddr);
                break;
        case RTL_GIGA_MAC_VER_20:
-               rtl8168cx_hw_phy_config(ioaddr);
+               rtl8168c_2_hw_phy_config(ioaddr);
                break;
        default:
                break;
@@ -2384,6 +2384,112 @@ static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
        }
 }
 
+static void rtl_disable_clock_request(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct rtl8169_private *tp = netdev_priv(dev);
+       int cap = tp->pcie_cap;
+
+       if (cap) {
+               u16 ctl;
+
+               pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
+               ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
+               pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
+       }
+}
+
+#define R8168_CPCMD_QUIRK_MASK (\
+       EnableBist | \
+       Mac_dbgo_oe | \
+       Force_half_dup | \
+       Force_rxflow_en | \
+       Force_txflow_en | \
+       Cxpl_dbg_sel | \
+       ASF | \
+       PktCntrDisable | \
+       Mac_dbgo_sel)
+
+static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
+
+       RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
+
+       rtl_tx_performance_tweak(pdev,
+               (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
+}
+
+static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       rtl_hw_start_8168bb(ioaddr, pdev);
+
+       RTL_W8(EarlyTxThres, EarlyTxThld);
+
+       RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
+}
+
+static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
+
+       RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
+
+       rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+
+       rtl_disable_clock_request(pdev);
+
+       RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
+}
+
+static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       static struct ephy_info e_info_8168cp[] = {
+               { 0x01, 0,      0x0001 },
+               { 0x02, 0x0800, 0x1000 },
+               { 0x03, 0,      0x0042 },
+               { 0x06, 0x0080, 0x0000 },
+               { 0x07, 0,      0x2000 }
+       };
+
+       rtl_csi_access_enable(ioaddr);
+
+       rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
+
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
+static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       static struct ephy_info e_info_8168c_1[] = {
+               { 0x02, 0x0800, 0x1000 },
+               { 0x03, 0,      0x0002 },
+               { 0x06, 0x0080, 0x0000 }
+       };
+
+       rtl_csi_access_enable(ioaddr);
+
+       RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
+
+       rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
+
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
+static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+       static struct ephy_info e_info_8168c_2[] = {
+               { 0x01, 0,      0x0001 },
+               { 0x03, 0x0400, 0x0220 }
+       };
+
+       rtl_csi_access_enable(ioaddr);
+
+       rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
+
+       __rtl_hw_start_8168cp(ioaddr, pdev);
+}
+
 static void rtl_hw_start_8168(struct net_device *dev)
 {
        struct rtl8169_private *tp = netdev_priv(dev);
@@ -2396,14 +2502,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
 
        rtl_set_rx_max_size(ioaddr);
 
-       rtl_set_rx_tx_config_registers(tp);
-
        tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
 
        RTL_W16(CPlusCmd, tp->cp_cmd);
 
-       rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
-
        RTL_W16(IntrMitigate, 0x5151);
 
        /* Work around for RxFIFO overflow. */
@@ -2414,14 +2516,45 @@ static void rtl_hw_start_8168(struct net_device *dev)
 
        rtl_set_rx_tx_desc_registers(tp, ioaddr);
 
-       RTL_W8(Cfg9346, Cfg9346_Lock);
+       rtl_set_rx_mode(dev);
+
+       RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
+               (InterFrameGap << TxInterFrameGapShift));
 
        RTL_R8(IntrMask);
 
-       rtl_set_rx_mode(dev);
+       switch (tp->mac_version) {
+       case RTL_GIGA_MAC_VER_11:
+               rtl_hw_start_8168bb(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_12:
+       case RTL_GIGA_MAC_VER_17:
+               rtl_hw_start_8168bef(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_18:
+               rtl_hw_start_8168cp(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_19:
+               rtl_hw_start_8168c_1(ioaddr, pdev);
+       break;
+
+       case RTL_GIGA_MAC_VER_20:
+               rtl_hw_start_8168c_2(ioaddr, pdev);
+       break;
+
+       default:
+               printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
+                       dev->name, tp->mac_version);
+       break;
+       }
 
        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 
+       RTL_W8(Cfg9346, Cfg9346_Lock);
+
        RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 
        RTL_W16(IntrMask, tp->intr_event);