tg3: Show flowctrl settings through get_settings()

[mirror_ubuntu-artful-kernel.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index db19332a7d87ae69ef2268b7c25901ec6f3aca5d..7b1e2abf0cea051016392976eb8c354d6f399759 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -26,6 +26,7 @@
 #include <linux/delay.h>
 #include <linux/in.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/pci.h>
 #include <linux/netdevice.h>
@@ -292,6 +293,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
        {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
+       {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
        {}
 };
 
@@ -5773,7 +5775,7 @@ static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
                         dma_unmap_addr(txb, mapping),
                         skb_headlen(skb),
                         PCI_DMA_TODEVICE);
-       for (i = 0; i <= last; i++) {
+       for (i = 0; i < last; i++) {
                skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
                entry = NEXT_TX(entry);
@@ -5820,8 +5822,7 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
                /* Make sure new skb does not cross any 4G boundaries.
                 * Drop the packet if it does.
                 */
-               } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
-                          tg3_4g_overflow_test(new_addr, new_skb->len)) {
+               } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
                        pci_unmap_single(tp->pdev, new_addr, new_skb->len,
                                         PCI_DMA_TODEVICE);
                        ret = -1;
@@ -6016,12 +6017,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
        if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
                would_hit_hwbug = 1;
 
-       if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
-           tg3_4g_overflow_test(mapping, len))
+       if (tg3_4g_overflow_test(mapping, len))
                would_hit_hwbug = 1;
 
-       if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
-           tg3_40bit_overflow_test(tp, mapping, len))
+       if (tg3_40bit_overflow_test(tp, mapping, len))
                would_hit_hwbug = 1;
 
        if (tg3_flag(tp, 5701_DMA_BUG))
@@ -6054,12 +6053,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
                            len <= 8)
                                would_hit_hwbug = 1;
 
-                       if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
-                           tg3_4g_overflow_test(mapping, len))
+                       if (tg3_4g_overflow_test(mapping, len))
                                would_hit_hwbug = 1;
 
-                       if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
-                           tg3_40bit_overflow_test(tp, mapping, len))
+                       if (tg3_40bit_overflow_test(tp, mapping, len))
                                would_hit_hwbug = 1;
 
                        if (tg3_flag(tp, HW_TSO_1) ||
@@ -6090,6 +6087,8 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
        /* Packets are ready, update Tx producer idx local and on card. */
        tw32_tx_mbox(tnapi->prodmbox, entry);
 
+       skb_tx_timestamp(skb);
+
        tnapi->tx_prod = entry;
        if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
                netif_tx_stop_queue(txq);
@@ -7750,6 +7749,9 @@ static void tg3_rings_reset(struct tg3 *tp)
 
        /* Disable interrupts */
        tw32_mailbox_f(tp->napi[0].int_mbox, 1);
+       tp->napi[0].chk_msi_cnt = 0;
+       tp->napi[0].last_rx_cons = 0;
+       tp->napi[0].last_tx_cons = 0;
 
        /* Zero mailbox registers. */
        if (tg3_flag(tp, SUPPORT_MSIX)) {
@@ -7760,6 +7762,9 @@ static void tg3_rings_reset(struct tg3 *tp)
                                tw32_mailbox(tp->napi[i].prodmbox, 0);
                        tw32_rx_mbox(tp->napi[i].consmbox, 0);
                        tw32_mailbox_f(tp->napi[i].int_mbox, 1);
+                       tp->napi[0].chk_msi_cnt = 0;
+                       tp->napi[i].last_rx_cons = 0;
+                       tp->napi[i].last_tx_cons = 0;
                }
                if (!tg3_flag(tp, ENABLE_TSS))
                        tw32_mailbox(tp->napi[0].prodmbox, 0);
@@ -8815,6 +8820,30 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
        TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
 }
 
+static void tg3_chk_missed_msi(struct tg3 *tp)
+{
+       u32 i;
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               if (tg3_has_work(tnapi)) {
+                       if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
+                           tnapi->last_tx_cons == tnapi->tx_cons) {
+                               if (tnapi->chk_msi_cnt < 1) {
+                                       tnapi->chk_msi_cnt++;
+                                       return;
+                               }
+                               tw32_mailbox(tnapi->int_mbox,
+                                            tnapi->last_tag << 24);
+                       }
+               }
+               tnapi->chk_msi_cnt = 0;
+               tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
+               tnapi->last_tx_cons = tnapi->tx_cons;
+       }
+}
+
 static void tg3_timer(unsigned long __opaque)
 {
        struct tg3 *tp = (struct tg3 *) __opaque;
@@ -8824,6 +8853,10 @@ static void tg3_timer(unsigned long __opaque)
 
        spin_lock(&tp->lock);
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               tg3_chk_missed_msi(tp);
+
        if (!tg3_flag(tp, TAGGED_STATUS)) {
                /* All of this garbage is because when using non-tagged
                 * IRQ status the mailbox/status_block protocol the chip
@@ -9299,7 +9332,9 @@ static int tg3_open(struct net_device *dev)
                tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
                tg3_free_rings(tp);
        } else {
-               if (tg3_flag(tp, TAGGED_STATUS))
+               if (tg3_flag(tp, TAGGED_STATUS) &&
+                       GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
+                       GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
                        tp->timer_offset = HZ;
                else
                        tp->timer_offset = HZ / 10;
@@ -9901,6 +9936,18 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        }
 
        cmd->advertising = tp->link_config.advertising;
+       if (tg3_flag(tp, PAUSE_AUTONEG)) {
+               if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
+                       if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
+                               cmd->advertising |= ADVERTISED_Pause;
+                       } else {
+                               cmd->advertising |= ADVERTISED_Pause |
+                                                   ADVERTISED_Asym_Pause;
+                       }
+               } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
+                       cmd->advertising |= ADVERTISED_Asym_Pause;
+               }
+       }
        if (netif_running(dev)) {
                ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
                cmd->duplex = tp->link_config.active_duplex;
@@ -10435,6 +10482,9 @@ error:
 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE  0x14
 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE  0x18
 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE  0x1c
+#define NVRAM_SELFBOOT_FORMAT1_4_SIZE  0x20
+#define NVRAM_SELFBOOT_FORMAT1_5_SIZE  0x24
+#define NVRAM_SELFBOOT_FORMAT1_6_SIZE  0x4c
 #define NVRAM_SELFBOOT_HW_SIZE 0x20
 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
 
@@ -10465,8 +10515,17 @@ static int tg3_test_nvram(struct tg3 *tp)
                        case TG3_EEPROM_SB_REVISION_3:
                                size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
                                break;
+                       case TG3_EEPROM_SB_REVISION_4:
+                               size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_5:
+                               size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_6:
+                               size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
+                               break;
                        default:
-                               return 0;
+                               return -EIO;
                        }
                } else
                        return 0;
@@ -13665,15 +13724,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                }
        }
 
-       /* All chips can get confused if TX buffers
-        * straddle the 4GB address boundary.
-        */
-       tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
-
        if (tg3_flag(tp, 5755_PLUS))
                tg3_flag_set(tp, SHORT_DMA_BUG);
-       else
-               tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
 
        if (tg3_flag(tp, 5717_PLUS))
                tg3_flag_set(tp, LRG_PROD_RING_CAP);