Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic...

[mirror_ubuntu-artful-kernel.git] / drivers / pci / host / pci-imx6.c

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index fdb95367721e9b2e9758ee9f05beb4c878374dbd..233a196c6e6661c8dc9aea975a5cf15bf253c2fb 100644 (file)
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -47,6 +47,8 @@ struct imx6_pcie {
 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2       0x2
 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK       0xf
 
+#define PCIE_RC_LCSR                           0x80
+
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET 0x700
 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
@@ -335,21 +337,36 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 
 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
 {
-       int count = 200;
+       unsigned int retries;
 
-       while (!dw_pcie_link_up(pp)) {
+       for (retries = 0; retries < 200; retries++) {
+               if (dw_pcie_link_up(pp))
+                       return 0;
                usleep_range(100, 1000);
-               if (--count)
-                       continue;
-
-               dev_err(pp->dev, "phy link never came up\n");
-               dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-                       readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
-                       readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
-               return -EINVAL;
        }
 
-       return 0;
+       dev_err(pp->dev, "phy link never came up\n");
+       dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+               readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
+               readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
+       return -EINVAL;
+}
+
+static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
+{
+       u32 tmp;
+       unsigned int retries;
+
+       for (retries = 0; retries < 200; retries++) {
+               tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+               /* Test if the speed change finished. */
+               if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
+                       return 0;
+               usleep_range(100, 1000);
+       }
+
+       dev_err(pp->dev, "Speed change timeout\n");
+       return -EINVAL;
 }
 
 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
@@ -359,11 +376,11 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
        return dw_handle_msi_irq(pp);
 }
 
-static int imx6_pcie_start_link(struct pcie_port *pp)
+static int imx6_pcie_establish_link(struct pcie_port *pp)
 {
        struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
-       uint32_t tmp;
-       int ret, count;
+       u32 tmp;
+       int ret;
 
        /*
         * Force Gen1 operation when starting the link.  In case the link is
@@ -397,29 +414,22 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
        tmp |= PORT_LOGIC_SPEED_CHANGE;
        writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 
-       count = 200;
-       while (count--) {
-               tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
-               /* Test if the speed change finished. */
-               if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
-                       break;
-               usleep_range(100, 1000);
+       ret = imx6_pcie_wait_for_speed_change(pp);
+       if (ret) {
+               dev_err(pp->dev, "Failed to bring link up!\n");
+               return ret;
        }
 
        /* Make sure link training is finished as well! */
-       if (count)
-               ret = imx6_pcie_wait_for_link(pp);
-       else
-               ret = -EINVAL;
-
+       ret = imx6_pcie_wait_for_link(pp);
        if (ret) {
                dev_err(pp->dev, "Failed to bring link up!\n");
-       } else {
-               tmp = readl(pp->dbi_base + 0x80);
-               dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
+               return ret;
        }
 
-       return ret;
+       tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
+       dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
+       return 0;
 }
 
 static void imx6_pcie_host_init(struct pcie_port *pp)
@@ -432,7 +442,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
 
        dw_pcie_setup_rc(pp);
 
-       imx6_pcie_start_link(pp);
+       imx6_pcie_establish_link(pp);
 
        if (IS_ENABLED(CONFIG_PCI_MSI))
                dw_pcie_msi_init(pp);
@@ -440,19 +450,19 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
 
 static void imx6_pcie_reset_phy(struct pcie_port *pp)
 {
-       uint32_t temp;
+       u32 tmp;
 
-       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
-       temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
-                PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
+       tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
+               PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
 
        usleep_range(2000, 3000);
 
-       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
-       temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
+       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
+       tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
                  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
 }
 
 static int imx6_pcie_link_up(struct pcie_port *pp)