pinctrl: tegra: Fix write barrier placement in pmx_writel

[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / samsung / pinctrl-exynos-arm.c

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 071084d3ee9c19606679ffcc280f8d7d8388ac1f..07eb4f071fa872470c7c61ac17d60ae615d6e48c 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -76,6 +76,7 @@ s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
        }
 
        clk_base = of_iomap(np, 0);
+       of_node_put(np);
        if (!clk_base) {
                pr_err("%s: failed to map clock registers\n", __func__);
                return ERR_PTR(-EINVAL);
@@ -110,12 +111,12 @@ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
        EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
        EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
-       EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
        EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
        EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
        EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
        EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
        EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
+       EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
        EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
        EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
        EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
@@ -129,7 +130,7 @@ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
        EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 };
 
-const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = s5pv210_pin_bank,
@@ -142,6 +143,11 @@ const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
+       .ctrl           = s5pv210_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(s5pv210_pin_ctrl),
+};
+
 /* Pad retention control code for accessing PMU regmap */
 static atomic_t exynos_shared_retention_refcnt;
 
@@ -204,7 +210,7 @@ static const struct samsung_retention_data exynos3250_retention_data __initconst
  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
  * two gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos3250_pin_banks0,
@@ -225,6 +231,11 @@ const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
+       .ctrl           = exynos3250_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos3250_pin_ctrl),
+};
+
 /* pin banks of exynos4210 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -308,7 +319,7 @@ static const struct samsung_retention_data exynos4_audio_retention_data __initco
  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
  * three gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos4210_pin_banks0,
@@ -334,6 +345,11 @@ const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
+       .ctrl           = exynos4210_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos4210_pin_ctrl),
+};
+
 /* pin banks of exynos4x12 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -396,7 +412,7 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst =
  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
  * four gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos4x12_pin_banks0,
@@ -432,6 +448,11 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
+       .ctrl           = exynos4x12_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos4x12_pin_ctrl),
+};
+
 /* pin banks of exynos5250 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -492,7 +513,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst =
  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
  * four gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos5250_pin_banks0,
@@ -528,6 +549,11 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
+       .ctrl           = exynos5250_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos5250_pin_ctrl),
+};
+
 /* pin banks of exynos5260 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
@@ -572,7 +598,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst =
  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
  * three gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos5260_pin_banks0,
@@ -592,6 +618,11 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
+       .ctrl           = exynos5260_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos5260_pin_ctrl),
+};
+
 /* pin banks of exynos5410 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -605,7 +636,6 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst =
        EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
        EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
        EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
-       EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
        EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
        EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
        EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
@@ -616,6 +646,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst =
        EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
        EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
        EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
+       EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
        EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
        EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
        EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
@@ -662,7 +693,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst =
  * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
  * four gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos5410_pin_banks0,
@@ -695,6 +726,11 @@ const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
        },
 };
 
+const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
+       .ctrl           = exynos5410_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos5410_pin_ctrl),
+};
+
 /* pin banks of exynos5420 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
@@ -779,7 +815,7 @@ static const struct samsung_retention_data exynos5420_retention_data __initconst
  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
  * four gpio/pin-mux/pinconfig controllers.
  */
-const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
+static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 data */
                .pin_banks      = exynos5420_pin_banks0,
@@ -813,3 +849,8 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
                .retention_data = &exynos4_audio_retention_data,
        },
 };
+
+const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
+       .ctrl           = exynos5420_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(exynos5420_pin_ctrl),
+};