drm/msm: Fix range size vs end confusion

[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-mt65xx.c

diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 386e8c84be0af24c951526554b37e24cfbc4ae79..2ca19b01948a2b51180e35aceb0ac302b1c5b59b 100644 (file)
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -43,8 +43,11 @@
 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
 #define SPI_CFG1_GET_TICK_DLY_OFFSET      29
+#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1   30
 
 #define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000
+#define SPI_CFG1_GET_TICK_DLY_MASK_V1     0xc0000000
+
 #define SPI_CFG1_CS_IDLE_MASK             0xff
 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
@@ -233,36 +236,44 @@ static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
                return delay;
        inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
 
-       setup    = setup ? setup : 1;
-       hold     = hold ? hold : 1;
-       inactive = inactive ? inactive : 1;
-
-       reg_val = readl(mdata->base + SPI_CFG0_REG);
-       if (mdata->dev_comp->enhance_timing) {
-               hold = min_t(u32, hold, 0x10000);
-               setup = min_t(u32, setup, 0x10000);
-               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
-               reg_val |= (((hold - 1) & 0xffff)
-                          << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
-               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
-               reg_val |= (((setup - 1) & 0xffff)
-                          << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
-       } else {
-               hold = min_t(u32, hold, 0x100);
-               setup = min_t(u32, setup, 0x100);
-               reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
-               reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
-               reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
-               reg_val |= (((setup - 1) & 0xff)
-                           << SPI_CFG0_CS_SETUP_OFFSET);
+       if (hold || setup) {
+               reg_val = readl(mdata->base + SPI_CFG0_REG);
+               if (mdata->dev_comp->enhance_timing) {
+                       if (hold) {
+                               hold = min_t(u32, hold, 0x10000);
+                               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
+                               reg_val |= (((hold - 1) & 0xffff)
+                                       << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
+                       }
+                       if (setup) {
+                               setup = min_t(u32, setup, 0x10000);
+                               reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
+                               reg_val |= (((setup - 1) & 0xffff)
+                                       << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
+                       }
+               } else {
+                       if (hold) {
+                               hold = min_t(u32, hold, 0x100);
+                               reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
+                               reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
+                       }
+                       if (setup) {
+                               setup = min_t(u32, setup, 0x100);
+                               reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
+                               reg_val |= (((setup - 1) & 0xff)
+                                       << SPI_CFG0_CS_SETUP_OFFSET);
+                       }
+               }
+               writel(reg_val, mdata->base + SPI_CFG0_REG);
        }
-       writel(reg_val, mdata->base + SPI_CFG0_REG);
 
-       inactive = min_t(u32, inactive, 0x100);
-       reg_val = readl(mdata->base + SPI_CFG1_REG);
-       reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
-       reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
-       writel(reg_val, mdata->base + SPI_CFG1_REG);
+       if (inactive) {
+               inactive = min_t(u32, inactive, 0x100);
+               reg_val = readl(mdata->base + SPI_CFG1_REG);
+               reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
+               reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
+               writel(reg_val, mdata->base + SPI_CFG1_REG);
+       }
 
        return 0;
 }
@@ -338,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *master,
 
        /* tick delay */
        reg_val = readl(mdata->base + SPI_CFG1_REG);
-       reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-       reg_val |= ((chip_config->tick_delay & 0x7)
-               << SPI_CFG1_GET_TICK_DLY_OFFSET);
+       if (mdata->dev_comp->enhance_timing) {
+               reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
+               reg_val |= ((chip_config->tick_delay & 0x7)
+                           << SPI_CFG1_GET_TICK_DLY_OFFSET);
+       } else {
+               reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
+               reg_val |= ((chip_config->tick_delay & 0x3)
+                           << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
+       }
        writel(reg_val, mdata->base + SPI_CFG1_REG);
 
        /* set hw cs timing */
@@ -616,7 +633,7 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
        else
                mdata->state = MTK_SPI_IDLE;
 
-       if (!master->can_dma(master, master->cur_msg->spi, trans)) {
+       if (!master->can_dma(master, NULL, trans)) {
                if (trans->rx_buf) {
                        cnt = mdata->xfer_len / 4;
                        ioread32_rep(mdata->base + SPI_RX_DATA_REG,