/* New register for SM750LE */
#define DE_STATE1 0x100054
-#define DE_STATE1_DE_ABORT 0:0
-#define DE_STATE1_DE_ABORT_OFF 0
-#define DE_STATE1_DE_ABORT_ON 1
+#define DE_STATE1_DE_ABORT BIT(0)
#define DE_STATE2 0x100058
-#define DE_STATE2_DE_FIFO 3:3
-#define DE_STATE2_DE_FIFO_NOTEMPTY 0
-#define DE_STATE2_DE_FIFO_EMPTY 1
-#define DE_STATE2_DE_STATUS 2:2
-#define DE_STATE2_DE_STATUS_IDLE 0
-#define DE_STATE2_DE_STATUS_BUSY 1
-#define DE_STATE2_DE_MEM_FIFO 1:1
-#define DE_STATE2_DE_MEM_FIFO_NOTEMPTY 0
-#define DE_STATE2_DE_MEM_FIFO_EMPTY 1
-#define DE_STATE2_DE_RESERVED 0:0
-
-
+#define DE_STATE2_DE_FIFO_EMPTY BIT(3)
+#define DE_STATE2_DE_STATUS_BUSY BIT(2)
+#define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
#define SYSTEM_CTRL 0x000000
-#define SYSTEM_CTRL_DPMS 31:30
-#define SYSTEM_CTRL_DPMS_VPHP 0
-#define SYSTEM_CTRL_DPMS_VPHN 1
-#define SYSTEM_CTRL_DPMS_VNHP 2
-#define SYSTEM_CTRL_DPMS_VNHN 3
-#define SYSTEM_CTRL_PCI_BURST 29:29
-#define SYSTEM_CTRL_PCI_BURST_OFF 0
-#define SYSTEM_CTRL_PCI_BURST_ON 1
-#define SYSTEM_CTRL_PCI_MASTER 25:25
-#define SYSTEM_CTRL_PCI_MASTER_OFF 0
-#define SYSTEM_CTRL_PCI_MASTER_ON 1
-#define SYSTEM_CTRL_LATENCY_TIMER 24:24
-#define SYSTEM_CTRL_LATENCY_TIMER_ON 0
-#define SYSTEM_CTRL_LATENCY_TIMER_OFF 1
-#define SYSTEM_CTRL_DE_FIFO 23:23
-#define SYSTEM_CTRL_DE_FIFO_NOTEMPTY 0
-#define SYSTEM_CTRL_DE_FIFO_EMPTY 1
-#define SYSTEM_CTRL_DE_STATUS 22:22
-#define SYSTEM_CTRL_DE_STATUS_IDLE 0
-#define SYSTEM_CTRL_DE_STATUS_BUSY 1
-#define SYSTEM_CTRL_DE_MEM_FIFO 21:21
-#define SYSTEM_CTRL_DE_MEM_FIFO_NOTEMPTY 0
-#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY 1
-#define SYSTEM_CTRL_CSC_STATUS 20:20
-#define SYSTEM_CTRL_CSC_STATUS_IDLE 0
-#define SYSTEM_CTRL_CSC_STATUS_BUSY 1
-#define SYSTEM_CTRL_CRT_VSYNC 19:19
-#define SYSTEM_CTRL_CRT_VSYNC_INACTIVE 0
-#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE 1
-#define SYSTEM_CTRL_PANEL_VSYNC 18:18
-#define SYSTEM_CTRL_PANEL_VSYNC_INACTIVE 0
-#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE 1
-#define SYSTEM_CTRL_CURRENT_BUFFER 17:17
-#define SYSTEM_CTRL_CURRENT_BUFFER_NORMAL 0
-#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING 1
-#define SYSTEM_CTRL_DMA_STATUS 16:16
-#define SYSTEM_CTRL_DMA_STATUS_IDLE 0
-#define SYSTEM_CTRL_DMA_STATUS_BUSY 1
-#define SYSTEM_CTRL_PCI_BURST_READ 15:15
-#define SYSTEM_CTRL_PCI_BURST_READ_OFF 0
-#define SYSTEM_CTRL_PCI_BURST_READ_ON 1
-#define SYSTEM_CTRL_DE_ABORT 13:13
-#define SYSTEM_CTRL_DE_ABORT_OFF 0
-#define SYSTEM_CTRL_DE_ABORT_ON 1
-#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK 11:11
-#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_OFF 0
-#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_ON 1
-#define SYSTEM_CTRL_PCI_RETRY 7:7
-#define SYSTEM_CTRL_PCI_RETRY_ON 0
-#define SYSTEM_CTRL_PCI_RETRY_OFF 1
-#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE 5:4
-#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 0
-#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 1
-#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 2
-#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 3
-#define SYSTEM_CTRL_CRT_TRISTATE 3:3
-#define SYSTEM_CTRL_CRT_TRISTATE_OFF 0
-#define SYSTEM_CTRL_CRT_TRISTATE_ON 1
-#define SYSTEM_CTRL_PCIMEM_TRISTATE 2:2
-#define SYSTEM_CTRL_PCIMEM_TRISTATE_OFF 0
-#define SYSTEM_CTRL_PCIMEM_TRISTATE_ON 1
-#define SYSTEM_CTRL_LOCALMEM_TRISTATE 1:1
-#define SYSTEM_CTRL_LOCALMEM_TRISTATE_OFF 0
-#define SYSTEM_CTRL_LOCALMEM_TRISTATE_ON 1
-#define SYSTEM_CTRL_PANEL_TRISTATE 0:0
-#define SYSTEM_CTRL_PANEL_TRISTATE_OFF 0
-#define SYSTEM_CTRL_PANEL_TRISTATE_ON 1
+#define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
+#define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
+#define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
+#define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
+#define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
+#define SYSTEM_CTRL_PCI_BURST BIT(29)
+#define SYSTEM_CTRL_PCI_MASTER BIT(25)
+#define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
+#define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
+#define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
+#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
+#define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20)
+#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19)
+#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18)
+#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17)
+#define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16)
+#define SYSTEM_CTRL_PCI_BURST_READ BIT(15)
+#define SYSTEM_CTRL_DE_ABORT BIT(13)
+#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11)
+#define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7)
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4)
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4)
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4)
+#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4)
+#define SYSTEM_CTRL_CRT_TRISTATE BIT(3)
+#define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2)
+#define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1)
+#define SYSTEM_CTRL_PANEL_TRISTATE BIT(0)
#define MISC_CTRL 0x000004
-#define MISC_CTRL_DRAM_RERESH_COUNT 27:27
-#define MISC_CTRL_DRAM_RERESH_COUNT_1ROW 0
-#define MISC_CTRL_DRAM_RERESH_COUNT_3ROW 1
+#define MISC_CTRL_DRAM_RERESH_COUNT BIT(27)
#define MISC_CTRL_DRAM_REFRESH_TIME 26:25
#define MISC_CTRL_DRAM_REFRESH_TIME_8 0
#define MISC_CTRL_DRAM_REFRESH_TIME_16 1
#define MISC_CTRL_DRAM_REFRESH_TIME_32 2
#define MISC_CTRL_DRAM_REFRESH_TIME_64 3
-#define MISC_CTRL_INT_OUTPUT 24:24
-#define MISC_CTRL_INT_OUTPUT_NORMAL 0
-#define MISC_CTRL_INT_OUTPUT_INVERT 1
-#define MISC_CTRL_PLL_CLK_COUNT 23:23
-#define MISC_CTRL_PLL_CLK_COUNT_OFF 0
-#define MISC_CTRL_PLL_CLK_COUNT_ON 1
-#define MISC_CTRL_DAC_POWER 20:20
-#define MISC_CTRL_DAC_POWER_ON 0
-#define MISC_CTRL_DAC_POWER_OFF 1
-#define MISC_CTRL_CLK_SELECT 16:16
-#define MISC_CTRL_CLK_SELECT_OSC 0
-#define MISC_CTRL_CLK_SELECT_TESTCLK 1
+#define MISC_CTRL_INT_OUTPUT_INVERT BIT(24)
+#define MISC_CTRL_PLL_CLK_COUNT BIT(23)
+#define MISC_CTRL_DAC_POWER_OFF BIT(20)
+#define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16)
#define MISC_CTRL_DRAM_COLUMN_SIZE 15:14
#define MISC_CTRL_DRAM_COLUMN_SIZE_256 0
#define MISC_CTRL_DRAM_COLUMN_SIZE_512 1
#define MISC_CTRL_LOCALMEM_SIZE_16M 0
#define MISC_CTRL_LOCALMEM_SIZE_32M 1
#define MISC_CTRL_LOCALMEM_SIZE_64M 2
-#define MISC_CTRL_DRAM_TWTR 11:11
-#define MISC_CTRL_DRAM_TWTR_2CLK 0
-#define MISC_CTRL_DRAM_TWTR_1CLK 1
-#define MISC_CTRL_DRAM_TWR 10:10
-#define MISC_CTRL_DRAM_TWR_3CLK 0
-#define MISC_CTRL_DRAM_TWR_2CLK 1
-#define MISC_CTRL_DRAM_TRP 9:9
-#define MISC_CTRL_DRAM_TRP_3CLK 0
-#define MISC_CTRL_DRAM_TRP_4CLK 1
-#define MISC_CTRL_DRAM_TRFC 8:8
-#define MISC_CTRL_DRAM_TRFC_12CLK 0
-#define MISC_CTRL_DRAM_TRFC_14CLK 1
-#define MISC_CTRL_DRAM_TRAS 7:7
-#define MISC_CTRL_DRAM_TRAS_7CLK 0
-#define MISC_CTRL_DRAM_TRAS_8CLK 1
-#define MISC_CTRL_LOCALMEM_RESET 6:6
-#define MISC_CTRL_LOCALMEM_RESET_RESET 0
-#define MISC_CTRL_LOCALMEM_RESET_NORMAL 1
-#define MISC_CTRL_LOCALMEM_STATE 5:5
-#define MISC_CTRL_LOCALMEM_STATE_ACTIVE 0
-#define MISC_CTRL_LOCALMEM_STATE_INACTIVE 1
-#define MISC_CTRL_CPU_CAS_LATENCY 4:4
-#define MISC_CTRL_CPU_CAS_LATENCY_2CLK 0
-#define MISC_CTRL_CPU_CAS_LATENCY_3CLK 1
-#define MISC_CTRL_DLL 3:3
-#define MISC_CTRL_DLL_ON 0
-#define MISC_CTRL_DLL_OFF 1
-#define MISC_CTRL_DRAM_OUTPUT 2:2
-#define MISC_CTRL_DRAM_OUTPUT_LOW 0
-#define MISC_CTRL_DRAM_OUTPUT_HIGH 1
-#define MISC_CTRL_LOCALMEM_BUS_SIZE 1:1
-#define MISC_CTRL_LOCALMEM_BUS_SIZE_32 0
-#define MISC_CTRL_LOCALMEM_BUS_SIZE_64 1
-#define MISC_CTRL_EMBEDDED_LOCALMEM 0:0
-#define MISC_CTRL_EMBEDDED_LOCALMEM_ON 0
-#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF 1
+#define MISC_CTRL_DRAM_TWTR BIT(11)
+#define MISC_CTRL_DRAM_TWR BIT(10)
+#define MISC_CTRL_DRAM_TRP BIT(9)
+#define MISC_CTRL_DRAM_TRFC BIT(8)
+#define MISC_CTRL_DRAM_TRAS BIT(7)
+#define MISC_CTRL_LOCALMEM_RESET BIT(6)
+#define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5)
+#define MISC_CTRL_CPU_CAS_LATENCY BIT(4)
+#define MISC_CTRL_DLL_OFF BIT(3)
+#define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2)
+#define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1)
+#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0)
#define GPIO_MUX 0x000008
-#define GPIO_MUX_31 31:31
-#define GPIO_MUX_31_GPIO 0
-#define GPIO_MUX_31_I2C 1
-#define GPIO_MUX_30 30:30
-#define GPIO_MUX_30_GPIO 0
-#define GPIO_MUX_30_I2C 1
-#define GPIO_MUX_29 29:29
-#define GPIO_MUX_29_GPIO 0
-#define GPIO_MUX_29_SSP1 1
-#define GPIO_MUX_28 28:28
-#define GPIO_MUX_28_GPIO 0
-#define GPIO_MUX_28_SSP1 1
-#define GPIO_MUX_27 27:27
-#define GPIO_MUX_27_GPIO 0
-#define GPIO_MUX_27_SSP1 1
-#define GPIO_MUX_26 26:26
-#define GPIO_MUX_26_GPIO 0
-#define GPIO_MUX_26_SSP1 1
-#define GPIO_MUX_25 25:25
-#define GPIO_MUX_25_GPIO 0
-#define GPIO_MUX_25_SSP1 1
-#define GPIO_MUX_24 24:24
-#define GPIO_MUX_24_GPIO 0
-#define GPIO_MUX_24_SSP0 1
-#define GPIO_MUX_23 23:23
-#define GPIO_MUX_23_GPIO 0
-#define GPIO_MUX_23_SSP0 1
-#define GPIO_MUX_22 22:22
-#define GPIO_MUX_22_GPIO 0
-#define GPIO_MUX_22_SSP0 1
-#define GPIO_MUX_21 21:21
-#define GPIO_MUX_21_GPIO 0
-#define GPIO_MUX_21_SSP0 1
-#define GPIO_MUX_20 20:20
-#define GPIO_MUX_20_GPIO 0
-#define GPIO_MUX_20_SSP0 1
-#define GPIO_MUX_19 19:19
-#define GPIO_MUX_19_GPIO 0
-#define GPIO_MUX_19_PWM 1
-#define GPIO_MUX_18 18:18
-#define GPIO_MUX_18_GPIO 0
-#define GPIO_MUX_18_PWM 1
-#define GPIO_MUX_17 17:17
-#define GPIO_MUX_17_GPIO 0
-#define GPIO_MUX_17_PWM 1
-#define GPIO_MUX_16 16:16
-#define GPIO_MUX_16_GPIO_ZVPORT 0
-#define GPIO_MUX_16_TEST_DATA 1
-#define GPIO_MUX_15 15:15
-#define GPIO_MUX_15_GPIO_ZVPORT 0
-#define GPIO_MUX_15_TEST_DATA 1
-#define GPIO_MUX_14 14:14
-#define GPIO_MUX_14_GPIO_ZVPORT 0
-#define GPIO_MUX_14_TEST_DATA 1
-#define GPIO_MUX_13 13:13
-#define GPIO_MUX_13_GPIO_ZVPORT 0
-#define GPIO_MUX_13_TEST_DATA 1
-#define GPIO_MUX_12 12:12
-#define GPIO_MUX_12_GPIO_ZVPORT 0
-#define GPIO_MUX_12_TEST_DATA 1
-#define GPIO_MUX_11 11:11
-#define GPIO_MUX_11_GPIO_ZVPORT 0
-#define GPIO_MUX_11_TEST_DATA 1
-#define GPIO_MUX_10 10:10
-#define GPIO_MUX_10_GPIO_ZVPORT 0
-#define GPIO_MUX_10_TEST_DATA 1
-#define GPIO_MUX_9 9:9
-#define GPIO_MUX_9_GPIO_ZVPORT 0
-#define GPIO_MUX_9_TEST_DATA 1
-#define GPIO_MUX_8 8:8
-#define GPIO_MUX_8_GPIO_ZVPORT 0
-#define GPIO_MUX_8_TEST_DATA 1
-#define GPIO_MUX_7 7:7
-#define GPIO_MUX_7_GPIO_ZVPORT 0
-#define GPIO_MUX_7_TEST_DATA 1
-#define GPIO_MUX_6 6:6
-#define GPIO_MUX_6_GPIO_ZVPORT 0
-#define GPIO_MUX_6_TEST_DATA 1
-#define GPIO_MUX_5 5:5
-#define GPIO_MUX_5_GPIO_ZVPORT 0
-#define GPIO_MUX_5_TEST_DATA 1
-#define GPIO_MUX_4 4:4
-#define GPIO_MUX_4_GPIO_ZVPORT 0
-#define GPIO_MUX_4_TEST_DATA 1
-#define GPIO_MUX_3 3:3
-#define GPIO_MUX_3_GPIO_ZVPORT 0
-#define GPIO_MUX_3_TEST_DATA 1
-#define GPIO_MUX_2 2:2
-#define GPIO_MUX_2_GPIO_ZVPORT 0
-#define GPIO_MUX_2_TEST_DATA 1
-#define GPIO_MUX_1 1:1
-#define GPIO_MUX_1_GPIO_ZVPORT 0
-#define GPIO_MUX_1_TEST_DATA 1
-#define GPIO_MUX_0 0:0
-#define GPIO_MUX_0_GPIO_ZVPORT 0
-#define GPIO_MUX_0_TEST_DATA 1
+#define GPIO_MUX_31 BIT(31)
+#define GPIO_MUX_30 BIT(30)
+#define GPIO_MUX_29 BIT(29)
+#define GPIO_MUX_28 BIT(28)
+#define GPIO_MUX_27 BIT(27)
+#define GPIO_MUX_26 BIT(26)
+#define GPIO_MUX_25 BIT(25)
+#define GPIO_MUX_24 BIT(24)
+#define GPIO_MUX_23 BIT(23)
+#define GPIO_MUX_22 BIT(22)
+#define GPIO_MUX_21 BIT(21)
+#define GPIO_MUX_20 BIT(20)
+#define GPIO_MUX_19 BIT(19)
+#define GPIO_MUX_18 BIT(18)
+#define GPIO_MUX_17 BIT(17)
+#define GPIO_MUX_16 BIT(16)
+#define GPIO_MUX_15 BIT(15)
+#define GPIO_MUX_14 BIT(14)
+#define GPIO_MUX_13 BIT(13)
+#define GPIO_MUX_12 BIT(12)
+#define GPIO_MUX_11 BIT(11)
+#define GPIO_MUX_10 BIT(10)
+#define GPIO_MUX_9 BIT(9)
+#define GPIO_MUX_8 BIT(8)
+#define GPIO_MUX_7 BIT(7)
+#define GPIO_MUX_6 BIT(6)
+#define GPIO_MUX_5 BIT(5)
+#define GPIO_MUX_4 BIT(4)
+#define GPIO_MUX_3 BIT(3)
+#define GPIO_MUX_2 BIT(2)
+#define GPIO_MUX_1 BIT(1)
+#define GPIO_MUX_0 BIT(0)
#define LOCALMEM_ARBITRATION 0x00000C
#define LOCALMEM_ARBITRATION_ROTATE 28:28
projects / mirror_ubuntu-hirsute-kernel.git / blobdiff