/*
* gdb server stub
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
RS_GETLINE,
RS_CHKSUM1,
RS_CHKSUM2,
+ RS_SYSCALL,
};
-/* XXX: This is not thread safe. Do we care? */
-static int gdbserver_fd = -1;
-
typedef struct GDBState {
CPUState *env; /* current CPU */
enum RSState state; /* parsing state */
- int fd;
char line_buf[4096];
int line_buf_index;
int line_csum;
+ char last_packet[4100];
+ int last_packet_len;
#ifdef CONFIG_USER_ONLY
+ int fd;
int running_state;
+#else
+ CharDriverState *chr;
#endif
} GDBState;
#ifdef CONFIG_USER_ONLY
+/* XXX: This is not thread safe. Do we care? */
+static int gdbserver_fd = -1;
+
/* XXX: remove this hack. */
static GDBState gdbserver_state;
-#endif
static int get_char(GDBState *s)
{
}
return ch;
}
+#endif
+
+/* GDB stub state for use by semihosting syscalls. */
+static GDBState *gdb_syscall_state;
+static gdb_syscall_complete_cb gdb_current_syscall_cb;
+
+enum {
+ GDB_SYS_UNKNOWN,
+ GDB_SYS_ENABLED,
+ GDB_SYS_DISABLED,
+} gdb_syscall_mode;
+
+/* If gdb is connected when the first semihosting syscall occurs then use
+ remote gdb syscalls. Otherwise use native file IO. */
+int use_gdb_syscalls(void)
+{
+ if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
+ gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
+ : GDB_SYS_DISABLED);
+ }
+ return gdb_syscall_mode == GDB_SYS_ENABLED;
+}
static void put_buffer(GDBState *s, const uint8_t *buf, int len)
{
+#ifdef CONFIG_USER_ONLY
int ret;
while (len > 0) {
len -= ret;
}
}
+#else
+ qemu_chr_write(s->chr, buf, len);
+#endif
}
static inline int fromhex(int v)
/* return -1 if error, 0 if OK */
static int put_packet(GDBState *s, char *buf)
{
- char buf1[3];
- int len, csum, ch, i;
+ int len, csum, i;
+ char *p;
#ifdef DEBUG_GDB
printf("reply='%s'\n", buf);
#endif
for(;;) {
- buf1[0] = '$';
- put_buffer(s, buf1, 1);
+ p = s->last_packet;
+ *(p++) = '$';
len = strlen(buf);
- put_buffer(s, buf, len);
+ memcpy(p, buf, len);
+ p += len;
csum = 0;
for(i = 0; i < len; i++) {
csum += buf[i];
}
- buf1[0] = '#';
- buf1[1] = tohex((csum >> 4) & 0xf);
- buf1[2] = tohex((csum) & 0xf);
+ *(p++) = '#';
+ *(p++) = tohex((csum >> 4) & 0xf);
+ *(p++) = tohex((csum) & 0xf);
- put_buffer(s, buf1, 3);
+ s->last_packet_len = p - s->last_packet;
+ put_buffer(s, s->last_packet, s->last_packet_len);
- ch = get_char(s);
- if (ch < 0)
+#ifdef CONFIG_USER_ONLY
+ i = get_char(s);
+ if (i < 0)
return -1;
- if (ch == '+')
+ if (i == '+')
break;
+#else
+ break;
+#endif
}
return 0;
}
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
- uint32_t *registers = (uint32_t *)mem_buf;
int i, fpus;
+ uint32_t *registers = (uint32_t *)mem_buf;
+
+#ifdef TARGET_X86_64
+ /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
+ uint64_t *registers64 = (uint64_t *)mem_buf;
+
+ if (env->hflags & HF_CS64_MASK) {
+ registers64[0] = tswap64(env->regs[R_EAX]);
+ registers64[1] = tswap64(env->regs[R_EBX]);
+ registers64[2] = tswap64(env->regs[R_ECX]);
+ registers64[3] = tswap64(env->regs[R_EDX]);
+ registers64[4] = tswap64(env->regs[R_ESI]);
+ registers64[5] = tswap64(env->regs[R_EDI]);
+ registers64[6] = tswap64(env->regs[R_EBP]);
+ registers64[7] = tswap64(env->regs[R_ESP]);
+ for(i = 8; i < 16; i++) {
+ registers64[i] = tswap64(env->regs[i]);
+ }
+ registers64[16] = tswap64(env->eip);
+
+ registers = (uint32_t *)®isters64[17];
+ registers[0] = tswap32(env->eflags);
+ registers[1] = tswap32(env->segs[R_CS].selector);
+ registers[2] = tswap32(env->segs[R_SS].selector);
+ registers[3] = tswap32(env->segs[R_DS].selector);
+ registers[4] = tswap32(env->segs[R_ES].selector);
+ registers[5] = tswap32(env->segs[R_FS].selector);
+ registers[6] = tswap32(env->segs[R_GS].selector);
+ /* XXX: convert floats */
+ for(i = 0; i < 8; i++) {
+ memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10);
+ }
+ registers[27] = tswap32(env->fpuc); /* fctrl */
+ fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
+ registers[28] = tswap32(fpus); /* fstat */
+ registers[29] = 0; /* ftag */
+ registers[30] = 0; /* fiseg */
+ registers[31] = 0; /* fioff */
+ registers[32] = 0; /* foseg */
+ registers[33] = 0; /* fooff */
+ registers[34] = 0; /* fop */
+ for(i = 0; i < 16; i++) {
+ memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], 16);
+ }
+ registers[99] = tswap32(env->mxcsr);
+
+ return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
+ }
+#endif
for(i = 0; i < 8; i++) {
registers[i] = env->regs[i];
registers[41] = 0; /* foseg */
registers[42] = 0; /* fooff */
registers[43] = 0; /* fop */
-
+
for(i = 0; i < 16; i++)
tswapls(®isters[i]);
for(i = 36; i < 44; i++)
}
/* nip, msr, ccr, lnk, ctr, xer, mq */
registers[96] = tswapl(env->nip);
- registers[97] = tswapl(do_load_msr(env));
+ registers[97] = tswapl(env->msr);
tmp = 0;
for (i = 0; i < 8; i++)
tmp |= env->crf[i] << (32 - ((i + 1) * 4));
registers[98] = tswapl(tmp);
registers[99] = tswapl(env->lr);
registers[100] = tswapl(env->ctr);
- registers[101] = tswapl(do_load_xer(env));
+ registers[101] = tswapl(ppc_load_xer(env));
registers[102] = 0;
return 103 * 4;
}
/* nip, msr, ccr, lnk, ctr, xer, mq */
env->nip = tswapl(registers[96]);
- do_store_msr(env, tswapl(registers[97]));
+ ppc_store_msr(env, tswapl(registers[97]));
registers[98] = tswapl(registers[98]);
for (i = 0; i < 8; i++)
env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
env->lr = tswapl(registers[99]);
env->ctr = tswapl(registers[100]);
- do_store_xer(env, tswapl(registers[101]));
+ ppc_store_xer(env, tswapl(registers[101]));
}
#elif defined (TARGET_SPARC)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
for (i = 0; i < 64; i += 2) {
uint64_t tmp;
- tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
- tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
- registers[i/2 + 32] = tmp;
+ tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
+ tmp |= *(uint32_t *)&env->fpr[i + 1];
+ registers[i / 2 + 32] = tswap64(tmp);
}
registers[64] = tswapl(env->pc);
registers[65] = tswapl(env->npc);
- registers[66] = tswapl(env->tstate[env->tl]);
+ registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
+ ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) |
+ GET_CWP64(env));
registers[67] = tswapl(env->fsr);
registers[68] = tswapl(env->fprs);
registers[69] = tswapl(env->y);
env->fsr = tswapl(registers[70]);
#else
for (i = 0; i < 64; i += 2) {
- *((uint32_t *)&env->fpr[i]) = tswap32(registers[i/2 + 32] >> 32);
- *((uint32_t *)&env->fpr[i + 1]) = tswap32(registers[i/2 + 32] & 0xffffffff);
+ uint64_t tmp;
+
+ tmp = tswap64(registers[i / 2 + 32]);
+ *((uint32_t *)&env->fpr[i]) = tmp >> 32;
+ *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
}
env->pc = tswapl(registers[64]);
env->npc = tswapl(registers[65]);
- env->tstate[env->tl] = tswapl(registers[66]);
+ {
+ uint64_t tmp = tswapl(registers[66]);
+
+ PUT_CCR(env, tmp >> 32);
+ env->asi = (tmp >> 24) & 0xff;
+ env->pstate = (tmp >> 8) & 0xfff;
+ PUT_CWP64(env, tmp & 0xff);
+ }
env->fsr = tswapl(registers[67]);
env->fprs = tswapl(registers[68]);
env->y = tswapl(registers[69]);
ptr += 8 * 12 + 4;
cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
}
+#elif defined (TARGET_M68K)
+static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
+{
+ int i;
+ uint8_t *ptr;
+ CPU_DoubleU u;
+
+ ptr = mem_buf;
+ /* D0-D7 */
+ for (i = 0; i < 8; i++) {
+ *(uint32_t *)ptr = tswapl(env->dregs[i]);
+ ptr += 4;
+ }
+ /* A0-A7 */
+ for (i = 0; i < 8; i++) {
+ *(uint32_t *)ptr = tswapl(env->aregs[i]);
+ ptr += 4;
+ }
+ *(uint32_t *)ptr = tswapl(env->sr);
+ ptr += 4;
+ *(uint32_t *)ptr = tswapl(env->pc);
+ ptr += 4;
+ /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
+ ColdFire has 8-bit double precision registers. */
+ for (i = 0; i < 8; i++) {
+ u.d = env->fregs[i];
+ *(uint32_t *)ptr = tswap32(u.l.upper);
+ *(uint32_t *)ptr = tswap32(u.l.lower);
+ }
+ /* FP control regs (not implemented). */
+ memset (ptr, 0, 3 * 4);
+ ptr += 3 * 4;
+
+ return ptr - mem_buf;
+}
+
+static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
+{
+ int i;
+ uint8_t *ptr;
+ CPU_DoubleU u;
+
+ ptr = mem_buf;
+ /* D0-D7 */
+ for (i = 0; i < 8; i++) {
+ env->dregs[i] = tswapl(*(uint32_t *)ptr);
+ ptr += 4;
+ }
+ /* A0-A7 */
+ for (i = 0; i < 8; i++) {
+ env->aregs[i] = tswapl(*(uint32_t *)ptr);
+ ptr += 4;
+ }
+ env->sr = tswapl(*(uint32_t *)ptr);
+ ptr += 4;
+ env->pc = tswapl(*(uint32_t *)ptr);
+ ptr += 4;
+ /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
+ ColdFire has 8-bit double precision registers. */
+ for (i = 0; i < 8; i++) {
+ u.l.upper = tswap32(*(uint32_t *)ptr);
+ u.l.lower = tswap32(*(uint32_t *)ptr);
+ env->fregs[i] = u.d;
+ }
+ /* FP control regs (not implemented). */
+ ptr += 3 * 4;
+}
#elif defined (TARGET_MIPS)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
ptr = mem_buf;
for (i = 0; i < 32; i++)
{
- *(uint32_t *)ptr = tswapl(env->gpr[i]);
- ptr += 4;
+ *(target_ulong *)ptr = tswapl(env->gpr[i][env->current_tc]);
+ ptr += sizeof(target_ulong);
}
- *(uint32_t *)ptr = tswapl(env->CP0_Status);
- ptr += 4;
+ *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
+ ptr += sizeof(target_ulong);
- *(uint32_t *)ptr = tswapl(env->LO);
- ptr += 4;
+ *(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]);
+ ptr += sizeof(target_ulong);
- *(uint32_t *)ptr = tswapl(env->HI);
- ptr += 4;
+ *(target_ulong *)ptr = tswapl(env->HI[0][env->current_tc]);
+ ptr += sizeof(target_ulong);
- *(uint32_t *)ptr = tswapl(env->CP0_BadVAddr);
- ptr += 4;
+ *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
+ ptr += sizeof(target_ulong);
- *(uint32_t *)ptr = tswapl(env->CP0_Cause);
- ptr += 4;
+ *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
+ ptr += sizeof(target_ulong);
- *(uint32_t *)ptr = tswapl(env->PC);
- ptr += 4;
+ *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
+ ptr += sizeof(target_ulong);
- /* 32 FP registers, fsr, fir, fp. Not yet implemented. */
+ if (env->CP0_Config1 & (1 << CP0C1_FP))
+ {
+ for (i = 0; i < 32; i++)
+ {
+ if (env->CP0_Status & (1 << CP0St_FR))
+ *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
+ else
+ *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
+ ptr += sizeof(target_ulong);
+ }
+
+ *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
+ ptr += sizeof(target_ulong);
+
+ *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
+ ptr += sizeof(target_ulong);
+ }
+
+ /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
+ *(target_ulong *)ptr = 0;
+ ptr += sizeof(target_ulong);
+
+ /* Registers for embedded use, we just pad them. */
+ for (i = 0; i < 16; i++)
+ {
+ *(target_ulong *)ptr = 0;
+ ptr += sizeof(target_ulong);
+ }
+
+ /* Processor ID. */
+ *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
+ ptr += sizeof(target_ulong);
return ptr - mem_buf;
}
+/* convert MIPS rounding mode in FCR31 to IEEE library */
+static unsigned int ieee_rm[] =
+ {
+ float_round_nearest_even,
+ float_round_to_zero,
+ float_round_up,
+ float_round_down
+ };
+#define RESTORE_ROUNDING_MODE \
+ set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
+
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
int i;
ptr = mem_buf;
for (i = 0; i < 32; i++)
{
- env->gpr[i] = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->gpr[i][env->current_tc] = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
}
- env->CP0_Status = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->CP0_Status = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
- env->LO = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->LO[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
- env->HI = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->HI[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
- env->CP0_BadVAddr = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
- env->CP0_Cause = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->CP0_Cause = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
- env->PC = tswapl(*(uint32_t *)ptr);
- ptr += 4;
+ env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
+
+ if (env->CP0_Config1 & (1 << CP0C1_FP))
+ {
+ for (i = 0; i < 32; i++)
+ {
+ if (env->CP0_Status & (1 << CP0St_FR))
+ env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
+ else
+ env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
+ ptr += sizeof(target_ulong);
+ }
+
+ env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
+ ptr += sizeof(target_ulong);
+
+ /* The remaining registers are assumed to be read-only. */
+
+ /* set rounding mode */
+ RESTORE_ROUNDING_MODE;
+
+#ifndef CONFIG_SOFTFLOAT
+ /* no floating point exception for native float */
+ SET_FP_ENABLE(env->fcr31, 0);
+#endif
+ }
}
#elif defined (TARGET_SH4)
+
+/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
+
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
uint32_t *ptr = (uint32_t *)mem_buf;
SAVE (env->mach);
SAVE (env->macl);
SAVE (env->sr);
- SAVE (0); /* TICKS */
- SAVE (0); /* STALLS */
- SAVE (0); /* CYCLES */
- SAVE (0); /* INSTS */
- SAVE (0); /* PLR */
-
+ SAVE (env->fpul);
+ SAVE (env->fpscr);
+ for (i = 0; i < 16; i++)
+ SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
+ SAVE (env->ssr);
+ SAVE (env->spc);
+ for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
+ for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
return ((uint8_t *)ptr - mem_buf);
}
LOAD (env->mach);
LOAD (env->macl);
LOAD (env->sr);
+ LOAD (env->fpul);
+ LOAD (env->fpscr);
+ for (i = 0; i < 16; i++)
+ LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
+ LOAD (env->ssr);
+ LOAD (env->spc);
+ for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
+ for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
+}
+#elif defined (TARGET_CRIS)
+
+static int cris_save_32 (unsigned char *d, uint32_t value)
+{
+ *d++ = (value);
+ *d++ = (value >>= 8);
+ *d++ = (value >>= 8);
+ *d++ = (value >>= 8);
+ return 4;
+}
+static int cris_save_16 (unsigned char *d, uint32_t value)
+{
+ *d++ = (value);
+ *d++ = (value >>= 8);
+ return 2;
+}
+static int cris_save_8 (unsigned char *d, uint32_t value)
+{
+ *d++ = (value);
+ return 1;
+}
+
+/* FIXME: this will bug on archs not supporting unaligned word accesses. */
+static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
+{
+ uint8_t *ptr = mem_buf;
+ uint8_t srs;
+ int i;
+
+ for (i = 0; i < 16; i++)
+ ptr += cris_save_32 (ptr, env->regs[i]);
+
+ srs = env->pregs[SR_SRS];
+
+ ptr += cris_save_8 (ptr, env->pregs[0]);
+ ptr += cris_save_8 (ptr, env->pregs[1]);
+ ptr += cris_save_32 (ptr, env->pregs[2]);
+ ptr += cris_save_8 (ptr, srs);
+ ptr += cris_save_16 (ptr, env->pregs[4]);
+
+ for (i = 5; i < 16; i++)
+ ptr += cris_save_32 (ptr, env->pregs[i]);
+
+ ptr += cris_save_32 (ptr, env->pc);
+
+ for (i = 0; i < 16; i++)
+ ptr += cris_save_32 (ptr, env->sregs[srs][i]);
+
+ return ((uint8_t *)ptr - mem_buf);
+}
+
+static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
+{
+ uint32_t *ptr = (uint32_t *)mem_buf;
+ int i;
+
+#define LOAD(x) (x)=*ptr++;
+ for (i = 0; i < 16; i++) LOAD(env->regs[i]);
+ LOAD (env->pc);
}
#else
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
const char *p;
int ch, reg_size, type;
char buf[4096];
- uint8_t mem_buf[2000];
+ uint8_t mem_buf[4096];
uint32_t *registers;
target_ulong addr, len;
-
+
#ifdef DEBUG_GDB
printf("command='%s'\n", line_buf);
#endif
#elif defined (TARGET_ARM)
env->regs[15] = addr;
#elif defined (TARGET_SH4)
- env->pc = addr;
+ env->pc = addr;
+#elif defined (TARGET_MIPS)
+ env->PC[env->current_tc] = addr;
+#elif defined (TARGET_CRIS)
+ env->pc = addr;
#endif
}
#ifdef CONFIG_USER_ONLY
return RS_IDLE;
case 's':
if (*p != '\0') {
- addr = strtoul(p, (char **)&p, 16);
+ addr = strtoull(p, (char **)&p, 16);
#if defined(TARGET_I386)
env->eip = addr;
#elif defined (TARGET_PPC)
#elif defined (TARGET_ARM)
env->regs[15] = addr;
#elif defined (TARGET_SH4)
- env->pc = addr;
+ env->pc = addr;
+#elif defined (TARGET_MIPS)
+ env->PC[env->current_tc] = addr;
+#elif defined (TARGET_CRIS)
+ env->pc = addr;
#endif
}
cpu_single_step(env, 1);
vm_start();
#endif
return RS_IDLE;
+ case 'F':
+ {
+ target_ulong ret;
+ target_ulong err;
+
+ ret = strtoull(p, (char **)&p, 16);
+ if (*p == ',') {
+ p++;
+ err = strtoull(p, (char **)&p, 16);
+ } else {
+ err = 0;
+ }
+ if (*p == ',')
+ p++;
+ type = *p;
+ if (gdb_current_syscall_cb)
+ gdb_current_syscall_cb(s->env, ret, err);
+ if (type == 'C') {
+ put_packet(s, "T02");
+ } else {
+#ifdef CONFIG_USER_ONLY
+ s->running_state = 1;
+#else
+ vm_start();
+#endif
+ }
+ }
+ break;
case 'g':
reg_size = cpu_gdb_read_registers(env, mem_buf);
memtohex(buf, mem_buf, reg_size);
if (cpu_breakpoint_insert(env, addr) < 0)
goto breakpoint_error;
put_packet(s, "OK");
+#ifndef CONFIG_USER_ONLY
+ } else if (type == 2) {
+ if (cpu_watchpoint_insert(env, addr) < 0)
+ goto breakpoint_error;
+ put_packet(s, "OK");
+#endif
} else {
breakpoint_error:
put_packet(s, "E22");
if (type == 0 || type == 1) {
cpu_breakpoint_remove(env, addr);
put_packet(s, "OK");
+#ifndef CONFIG_USER_ONLY
+ } else if (type == 2) {
+ cpu_watchpoint_remove(env, addr);
+ put_packet(s, "OK");
+#endif
} else {
goto breakpoint_error;
}
break;
-#ifdef CONFIG_USER_ONLY
+#ifdef CONFIG_LINUX_USER
case 'q':
if (strncmp(p, "Offsets", 7) == 0) {
TaskState *ts = env->opaque;
- sprintf(buf, "Text=%x;Data=%x;Bss=%x", ts->info->code_offset,
- ts->info->data_offset, ts->info->data_offset);
+ sprintf(buf,
+ "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
+ ";Bss=" TARGET_ABI_FMT_lx,
+ ts->info->code_offset,
+ ts->info->data_offset,
+ ts->info->data_offset);
put_packet(s, buf);
break;
}
char buf[256];
int ret;
+ if (s->state == RS_SYSCALL)
+ return;
+
/* disable single step if it was enable */
cpu_single_step(s->env, 0);
if (reason == EXCP_DEBUG) {
+ if (s->env->watchpoint_hit) {
+ snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
+ SIGTRAP,
+ s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
+ put_packet(s, buf);
+ s->env->watchpoint_hit = 0;
+ return;
+ }
tb_flush(s->env);
ret = SIGTRAP;
} else if (reason == EXCP_INTERRUPT) {
}
#endif
+/* Send a gdb syscall request.
+ This accepts limited printf-style format specifiers, specifically:
+ %x - target_ulong argument printed in hex.
+ %lx - 64-bit argument printed in hex.
+ %s - string pointer (target_ulong) and length (int) pair. */
+void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
+{
+ va_list va;
+ char buf[256];
+ char *p;
+ target_ulong addr;
+ uint64_t i64;
+ GDBState *s;
+
+ s = gdb_syscall_state;
+ if (!s)
+ return;
+ gdb_current_syscall_cb = cb;
+ s->state = RS_SYSCALL;
+#ifndef CONFIG_USER_ONLY
+ vm_stop(EXCP_DEBUG);
+#endif
+ s->state = RS_IDLE;
+ va_start(va, fmt);
+ p = buf;
+ *(p++) = 'F';
+ while (*fmt) {
+ if (*fmt == '%') {
+ fmt++;
+ switch (*fmt++) {
+ case 'x':
+ addr = va_arg(va, target_ulong);
+ p += sprintf(p, TARGET_FMT_lx, addr);
+ break;
+ case 'l':
+ if (*(fmt++) != 'x')
+ goto bad_format;
+ i64 = va_arg(va, uint64_t);
+ p += sprintf(p, "%" PRIx64, i64);
+ break;
+ case 's':
+ addr = va_arg(va, target_ulong);
+ p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
+ break;
+ default:
+ bad_format:
+ fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
+ fmt - 1);
+ break;
+ }
+ } else {
+ *(p++) = *(fmt++);
+ }
+ }
+ *p = 0;
+ va_end(va);
+ put_packet(s, buf);
+#ifdef CONFIG_USER_ONLY
+ gdb_handlesig(s->env, 0);
+#else
+ cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
+#endif
+}
+
static void gdb_read_byte(GDBState *s, int ch)
{
CPUState *env = s->env;
char reply[1];
#ifndef CONFIG_USER_ONLY
+ if (s->last_packet_len) {
+ /* Waiting for a response to the last packet. If we see the start
+ of a new command then abandon the previous response. */
+ if (ch == '-') {
+#ifdef DEBUG_GDB
+ printf("Got NACK, retransmitting\n");
+#endif
+ put_buffer(s, s->last_packet, s->last_packet_len);
+ }
+#ifdef DEBUG_GDB
+ else if (ch == '+')
+ printf("Got ACK\n");
+ else
+ printf("Got '%c' when expecting ACK/NACK\n", ch);
+#endif
+ if (ch == '+' || ch == '$')
+ s->last_packet_len = 0;
+ if (ch != '$')
+ return;
+ }
if (vm_running) {
/* when the CPU is running, we cannot do anything except stop
it when receiving a char */
vm_stop(EXCP_INTERRUPT);
- } else
+ } else
#endif
{
switch(s->state) {
s->state = gdb_handle_packet(s, env, s->line_buf);
}
break;
+ default:
+ abort();
}
}
}
put_packet(s, buf);
}
-#else
-static void gdb_read(void *opaque)
-{
- GDBState *s = opaque;
- int i, size;
- uint8_t buf[4096];
-
- size = recv(s->fd, buf, sizeof(buf), 0);
- if (size < 0)
- return;
- if (size == 0) {
- /* end of connection */
- qemu_del_vm_stop_handler(gdb_vm_stopped, s);
- qemu_set_fd_handler(s->fd, NULL, NULL, NULL);
- qemu_free(s);
- vm_start();
- } else {
- for(i = 0; i < size; i++)
- gdb_read_byte(s, buf[i]);
- }
-}
-
-#endif
static void gdb_accept(void *opaque)
{
/* set short latency */
val = 1;
setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
-
-#ifdef CONFIG_USER_ONLY
+
s = &gdbserver_state;
memset (s, 0, sizeof (GDBState));
-#else
- s = qemu_mallocz(sizeof(GDBState));
- if (!s) {
- close(fd);
- return;
- }
-#endif
s->env = first_cpu; /* XXX: allow to change CPU */
s->fd = fd;
-#ifdef CONFIG_USER_ONLY
- fcntl(fd, F_SETFL, O_NONBLOCK);
-#else
- socket_set_nonblock(fd);
-
- /* stop the VM */
- vm_stop(EXCP_INTERRUPT);
+ gdb_syscall_state = s;
- /* start handling I/O */
- qemu_set_fd_handler(s->fd, gdb_read, NULL, s);
- /* when the VM is stopped, the following callback is called */
- qemu_add_vm_stop_handler(gdb_vm_stopped, s);
-#endif
+ fcntl(fd, F_SETFL, O_NONBLOCK);
}
static int gdbserver_open(int port)
perror("listen");
return -1;
}
-#ifndef CONFIG_USER_ONLY
- socket_set_nonblock(fd);
-#endif
return fd;
}
if (gdbserver_fd < 0)
return -1;
/* accept connections */
-#ifdef CONFIG_USER_ONLY
gdb_accept (NULL);
+ return 0;
+}
#else
- qemu_set_fd_handler(gdbserver_fd, gdb_accept, NULL, NULL);
-#endif
+static int gdb_chr_can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
+{
+ GDBState *s = opaque;
+ int i;
+
+ for (i = 0; i < size; i++) {
+ gdb_read_byte(s, buf[i]);
+ }
+}
+
+static void gdb_chr_event(void *opaque, int event)
+{
+ switch (event) {
+ case CHR_EVENT_RESET:
+ vm_stop(EXCP_INTERRUPT);
+ gdb_syscall_state = opaque;
+ break;
+ default:
+ break;
+ }
+}
+
+int gdbserver_start(const char *port)
+{
+ GDBState *s;
+ char gdbstub_port_name[128];
+ int port_num;
+ char *p;
+ CharDriverState *chr;
+
+ if (!port || !*port)
+ return -1;
+
+ port_num = strtol(port, &p, 10);
+ if (*p == 0) {
+ /* A numeric value is interpreted as a port number. */
+ snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
+ "tcp::%d,nowait,nodelay,server", port_num);
+ port = gdbstub_port_name;
+ }
+
+ chr = qemu_chr_open(port);
+ if (!chr)
+ return -1;
+
+ s = qemu_mallocz(sizeof(GDBState));
+ if (!s) {
+ return -1;
+ }
+ s->env = first_cpu; /* XXX: allow to change CPU */
+ s->chr = chr;
+ qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
+ gdb_chr_event, s);
+ qemu_add_vm_stop_handler(gdb_vm_stopped, s);
return 0;
}
+#endif
projects / mirror_qemu.git / blobdiff