#include "range.h"
#include "ioport.h"
#include "fw_cfg.h"
+#include "exec-memory.h"
//#define DEBUG
# define PIIX4_DPRINTF(format, ...) do { } while (0)
#endif
-#define ACPI_DBG_IO_ADDR 0xb044
-
#define GPE_BASE 0xafe0
#define GPE_LEN 4
+
+#define PCI_HOTPLUG_ADDR 0xae00
+#define PCI_HOTPLUG_SIZE 0x000f
#define PCI_UP_BASE 0xae00
#define PCI_DOWN_BASE 0xae04
#define PCI_EJ_BASE 0xae08
typedef struct PIIX4PMState {
PCIDevice dev;
- IORange ioport;
+ MemoryRegion io;
+ MemoryRegion io_gpe;
+ MemoryRegion io_pci;
ACPIREGS ar;
APMState apm;
pm_update_sci(s);
}
-static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
- uint64_t val)
-{
- PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
-
- if (width != 2) {
- PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
- (unsigned)addr, width, (unsigned)val);
- }
-
- switch(addr) {
- case 0x00:
- acpi_pm1_evt_write_sts(&s->ar, val);
- pm_update_sci(s);
- break;
- case 0x02:
- acpi_pm1_evt_write_en(&s->ar, val);
- pm_update_sci(s);
- break;
- case 0x04:
- acpi_pm1_cnt_write(&s->ar, val, s->s4_val);
- break;
- default:
- break;
- }
- PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
- (unsigned int)val);
-}
-
-static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
- uint64_t *data)
-{
- PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
- uint32_t val;
-
- switch(addr) {
- case 0x00:
- val = acpi_pm1_evt_get_sts(&s->ar);
- break;
- case 0x02:
- val = s->ar.pm1.evt.en;
- break;
- case 0x04:
- val = s->ar.pm1.cnt.cnt;
- break;
- case 0x08:
- val = acpi_pm_tmr_get(&s->ar);
- break;
- default:
- val = 0;
- break;
- }
- PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
- *data = val;
-}
-
-static const IORangeOps pm_iorange_ops = {
- .read = pm_ioport_read,
- .write = pm_ioport_write,
-};
-
static void apm_ctrl_changed(uint32_t val, void *arg)
{
PIIX4PMState *s = arg;
}
}
-static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
-{
- PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
-}
-
static void pm_io_space_update(PIIX4PMState *s)
{
uint32_t pm_io_base;
- if (s->dev.config[0x80] & 1) {
- pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
- pm_io_base &= 0xffc0;
+ pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
+ pm_io_base &= 0xffc0;
- /* XXX: need to improve memory and ioport allocation */
- PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
- iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
- ioport_register(&s->ioport);
- }
+ memory_region_transaction_begin();
+ memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
+ memory_region_set_address(&s->io, pm_io_base);
+ memory_region_transaction_commit();
+}
+
+static void smbus_io_space_update(PIIX4PMState *s)
+{
+ s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90));
+ s->smb_io_base &= 0xffc0;
+
+ memory_region_transaction_begin();
+ memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
+ memory_region_set_address(&s->smb.io, s->smb_io_base);
+ memory_region_transaction_commit();
}
static void pm_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(d, address, val, len);
- if (range_covers_byte(address, len, 0x80))
+ if (range_covers_byte(address, len, 0x80) ||
+ ranges_overlap(address, len, 0x40, 4)) {
pm_io_space_update((PIIX4PMState *)d);
+ }
+ if (range_covers_byte(address, len, 0xd2) ||
+ ranges_overlap(address, len, 0x90, 4)) {
+ smbus_io_space_update((PIIX4PMState *)d);
+ }
}
static void vmstate_pci_status_pre_save(void *opaque)
/* APM */
apm_init(dev, &s->apm, apm_ctrl_changed, s);
- register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
-
if (s->kvm_enabled) {
/* Mark SMM as already inited to prevent SMM from running. KVM does not
* support SMM mode. */
pci_conf[0x90] = s->smb_io_base | 1;
pci_conf[0x91] = s->smb_io_base >> 8;
pci_conf[0xd2] = 0x09;
- register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
- register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
+ pm_smbus_init(&s->dev.qdev, &s->smb);
+ memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
+ memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
+
+ memory_region_init(&s->io, "piix4-pm", 64);
+ memory_region_set_enabled(&s->io, false);
+ memory_region_add_subregion(get_system_io(), 0, &s->io);
- acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
+ acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
+ acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
+ acpi_pm1_cnt_init(&s->ar, &s->io);
acpi_gpe_init(&s->ar, GPE_LEN);
s->powerdown_notifier.notify = piix4_pm_powerdown_req;
qemu_register_powerdown_notifier(&s->powerdown_notifier);
- pm_smbus_init(&s->dev.qdev, &s->smb);
s->machine_ready.notify = piix4_pm_machine_ready;
qemu_add_machine_init_done_notifier(&s->machine_ready);
qemu_register_reset(piix4_reset, s);
s = DO_UPCAST(PIIX4PMState, dev, dev);
s->irq = sci_irq;
- acpi_pm1_cnt_init(&s->ar);
s->smi_irq = smi_irq;
s->kvm_enabled = kvm_enabled;
type_init(piix4_pm_register_types)
-static uint32_t gpe_readb(void *opaque, uint32_t addr)
+static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
PIIX4PMState *s = opaque;
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
return val;
}
-static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
+static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
{
PIIX4PMState *s = opaque;
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
}
+static const MemoryRegionOps piix4_gpe_ops = {
+ .read = gpe_readb,
+ .write = gpe_writeb,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static uint32_t pci_up_read(void *opaque, uint32_t addr)
{
PIIX4PMState *s = opaque;
return s->pci0_hotplug_enable;
}
+static const MemoryRegionOps piix4_pci_ops = {
+ .old_portio = (MemoryRegionPortio[]) {
+ {
+ .offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
+ .read = pci_up_read,
+ },{
+ .offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
+ .read = pci_down_read,
+ },{
+ .offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
+ .read = pci_features_read,
+ .write = pciej_write,
+ },{
+ .offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
+ .read = pcirmv_read,
+ },
+ PORTIO_END_OF_LIST()
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
PCIHotplugState state);
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
{
-
- register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
- register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
- acpi_gpe_blk(&s->ar, GPE_BASE);
-
- register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
- register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
-
- register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
- register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
-
- register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
-
+ memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0",
+ GPE_LEN);
+ memory_region_add_subregion(get_system_io(), GPE_BASE, &s->io_gpe);
+
+ memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug",
+ PCI_HOTPLUG_SIZE);
+ memory_region_add_subregion(get_system_io(), PCI_HOTPLUG_ADDR,
+ &s->io_pci);
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
}
projects / mirror_qemu.git / blobdiff