*/
#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
-#include "hw/hw.h"
-#include "hw/devices.h"
-#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
#include "alpha_sys.h"
#include "exec/address-spaces.h"
+#include "qom/object.h"
#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
TyphoonWindow win[4];
} TyphoonPchip;
-#define TYPHOON_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(TyphoonState, TYPHOON_PCI_HOST_BRIDGE)
-typedef struct TyphoonState {
+struct TyphoonState {
PCIHostState parent_obj;
TyphoonCchip cchip;
TyphoonPchip pchip;
MemoryRegion dchip_region;
- MemoryRegion ram_region;
-} TyphoonState;
+};
/* Called when one of DRIR or DIM changes. */
static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
}
}
-static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult cchip_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
{
CPUState *cpu = current_cpu;
TyphoonState *s = opaque;
break;
default:
- cpu_unassigned_access(cpu, addr, false, false, 0, size);
- return -1;
+ return MEMTX_ERROR;
}
- return ret;
+ *data = ret;
+ return MEMTX_OK;
}
static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
return 0;
}
-static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
{
TyphoonState *s = opaque;
uint64_t ret = 0;
break;
default:
- cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
- return -1;
+ return MEMTX_ERROR;
}
- return ret;
+ *data = ret;
+ return MEMTX_OK;
}
-static void cchip_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
+static MemTxResult cchip_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
{
TyphoonState *s = opaque;
uint64_t oldval, newval;
break;
default:
- cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
- return;
+ return MEMTX_ERROR;
}
+
+ return MEMTX_OK;
}
static void dchip_write(void *opaque, hwaddr addr,
/* Skip this. It's all related to DRAM timing and setup. */
}
-static void pchip_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
+static MemTxResult pchip_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
{
TyphoonState *s = opaque;
uint64_t oldval;
break;
default:
- cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
- return;
+ return MEMTX_ERROR;
}
+
+ return MEMTX_OK;
}
static const MemoryRegionOps cchip_ops = {
- .read = cchip_read,
- .write = cchip_write,
+ .read_with_attrs = cchip_read,
+ .write_with_attrs = cchip_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 8,
};
static const MemoryRegionOps pchip_ops = {
- .read = pchip_read,
- .write = pchip_write,
+ .read_with_attrs = pchip_read,
+ .write_with_attrs = pchip_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 8,
pte_addr |= (addr & (wsm | 0xfe000)) >> 10;
return pte_translate(pte_addr, ret);
} else {
- /* Direct-mapped translation. */
- return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
+ /* Direct-mapped translation. */
+ return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
}
}
/* Check the fourth window for DAC disable. */
if ((pchip->win[3].wba & 0x80000000000ull) == 0
- && window_translate(&pchip->win[3], addr, &ret)) {
+ && window_translate(&pchip->win[3], addr, &ret)) {
goto success;
}
} else {
if (pchip->ctl & 0x40) {
/* See 10.1.4.4; in particular <39:35> is ignored. */
make_iommu_tlbe(0, 0x007ffffffffull, &ret);
- goto success;
+ goto success;
}
}
pte_addr = pchip->win[3].tba & 0x7ffc00000ull;
pte_addr |= (addr & 0xffffe000u) >> 10;
if (pte_translate(pte_addr, &ret)) {
- goto success;
- }
+ goto success;
+ }
}
}
}
cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);
}
-PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
- qemu_irq *p_rtc_irq,
+PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq,
AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
{
- const uint64_t MB = 1024 * 1024;
- const uint64_t GB = 1024 * MB;
MemoryRegion *addr_space = get_system_memory();
DeviceState *dev;
TyphoonState *s;
PCIBus *b;
int i;
- dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_TYPHOON_PCI_HOST_BRIDGE);
s = TYPHOON_PCI_HOST_BRIDGE(dev);
phb = PCI_HOST_BRIDGE(dev);
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
but the address space hole reserved at this point is 8TB. */
- memory_region_allocate_system_memory(&s->ram_region, OBJECT(s), "ram",
- ram_size);
- memory_region_add_subregion(addr_space, 0, &s->ram_region);
+ memory_region_add_subregion(addr_space, 0, ram);
/* TIGbus, 0x801.0000.0000, 1GB. */
/* ??? The TIGbus is used for delivering interrupts, and access to
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
- 256*MB);
+ 256 * MiB);
memory_region_add_subregion(addr_space, 0x80180000000ULL,
&s->pchip.region);
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
- 256*MB);
+ 256 * MiB);
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
&s->cchip.region);
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
- 256*MB);
+ 256 * MiB);
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
&s->dchip_region);
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
- memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);
+ memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4 * GiB);
memory_region_add_subregion(addr_space, 0x80000000000ULL,
&s->pchip.reg_mem);
/* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops,
- NULL, "pci0-io", 32*MB);
+ NULL, "pci0-io", 32 * MiB);
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io);
&s->pchip.reg_mem, &s->pchip.reg_io,
0, 64, TYPE_PCI_BUS);
phb->bus = b;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Host memory as seen from the PCI side, via the IOMMU. */
memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,
- b, "pci0-iack", 64*MB);
+ b, "pci0-iack", 64 * MiB);
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
&s->pchip.reg_iack);
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops,
- b, "pci0-conf", 16*MB);
+ b, "pci0-conf", 16 * MiB);
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
&s->pchip.reg_conf);
return b;
}
-static int typhoon_pcihost_init(SysBusDevice *dev)
-{
- return 0;
-}
-
-static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-
- k->init = typhoon_pcihost_init;
-}
-
static const TypeInfo typhoon_pcihost_info = {
.name = TYPE_TYPHOON_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(TyphoonState),
- .class_init = typhoon_pcihost_class_init,
};
static void typhoon_iommu_memory_region_class_init(ObjectClass *klass,
projects / mirror_qemu.git / blobdiff