#include "hw/char/pl011.h"
#include "hw/hw.h"
#include "hw/irq.h"
+#include "hw/sd/sd.h"
+#include "qom/object.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
-#define INTEGRATOR_CM(obj) \
- OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
+typedef struct IntegratorCMState IntegratorCMState;
+DECLARE_INSTANCE_CHECKER(IntegratorCMState, INTEGRATOR_CM,
+ TYPE_INTEGRATOR_CM)
-typedef struct IntegratorCMState {
+struct IntegratorCMState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t int_level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
-} IntegratorCMState;
+};
static uint8_t integrator_spd[128] = {
128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
/* Primary interrupt controller. */
#define TYPE_INTEGRATOR_PIC "integrator_pic"
-#define INTEGRATOR_PIC(obj) \
- OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
+typedef struct icp_pic_state icp_pic_state;
+DECLARE_INSTANCE_CHECKER(icp_pic_state, INTEGRATOR_PIC,
+ TYPE_INTEGRATOR_PIC)
-typedef struct icp_pic_state {
+struct icp_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t fiq_enabled;
qemu_irq parent_irq;
qemu_irq parent_fiq;
-} icp_pic_state;
+};
static const VMStateDescription vmstate_icp_pic = {
.name = "icp_pic",
/* CP control registers. */
#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
-#define ICP_CONTROL_REGS(obj) \
- OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
+typedef struct ICPCtrlRegsState ICPCtrlRegsState;
+DECLARE_INSTANCE_CHECKER(ICPCtrlRegsState, ICP_CONTROL_REGS,
+ TYPE_ICP_CONTROL_REGS)
-typedef struct ICPCtrlRegsState {
+struct ICPCtrlRegsState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq mmc_irq;
uint32_t intreg_state;
-} ICPCtrlRegsState;
+};
#define ICP_GPIO_MMC_WPROT "mmc-wprot"
#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
DeviceState *dev, *sic, *icp;
+ DriveInfo *dinfo;
int i;
cpuobj = object_new(machine->cpu_type);
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
- object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
+ object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
}
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
- qdev_connect_gpio_out(dev, 0,
+ qdev_connect_gpio_out_named(dev, "card-read-only", 0,
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
- qdev_connect_gpio_out(dev, 1,
+ qdev_connect_gpio_out_named(dev, "card-inserted", 0,
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
+ dinfo = drive_get_next(IF_SD);
+ if (dinfo) {
+ DeviceState *card;
+
+ card = qdev_new(TYPE_SD_CARD);
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
+ &error_fatal);
+ }
+
sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
if (nd_table[0].used)