#include "hw/net/smc91c111.h"
#include "net/net.h"
#include "exec/address-spaces.h"
+#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
+#include "qemu/log.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
#include "hw/hw.h"
#include "hw/irq.h"
+#include "hw/sd/sd.h"
+#include "qom/object.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
-#define INTEGRATOR_CM(obj) \
- OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
+typedef struct IntegratorCMState IntegratorCMState;
+DECLARE_INSTANCE_CHECKER(IntegratorCMState, INTEGRATOR_CM,
+ TYPE_INTEGRATOR_CM)
-typedef struct IntegratorCMState {
+struct IntegratorCMState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t int_level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
-} IntegratorCMState;
+};
static uint8_t integrator_spd[128] = {
128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
/* ??? Voltage control unimplemented. */
return 0;
default:
- hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
- (int)offset);
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
return 0;
}
}
/* ??? Voltage control unimplemented. */
break;
default:
- hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
- (int)offset);
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
break;
}
}
/* Primary interrupt controller. */
#define TYPE_INTEGRATOR_PIC "integrator_pic"
-#define INTEGRATOR_PIC(obj) \
- OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
+typedef struct icp_pic_state icp_pic_state;
+DECLARE_INSTANCE_CHECKER(icp_pic_state, INTEGRATOR_PIC,
+ TYPE_INTEGRATOR_PIC)
-typedef struct icp_pic_state {
+struct icp_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t fiq_enabled;
qemu_irq parent_irq;
qemu_irq parent_fiq;
-} icp_pic_state;
+};
static const VMStateDescription vmstate_icp_pic = {
.name = "icp_pic",
case 5: /* INT_SOFTCLR */
case 11: /* FRQ_ENABLECLR */
default:
- printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
return 0;
}
}
case 8: /* FRQ_STATUS */
case 9: /* FRQ_RAWSTAT */
default:
- printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
return;
}
icp_pic_update(s);
/* CP control registers. */
#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
-#define ICP_CONTROL_REGS(obj) \
- OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
+typedef struct ICPCtrlRegsState ICPCtrlRegsState;
+DECLARE_INSTANCE_CHECKER(ICPCtrlRegsState, ICP_CONTROL_REGS,
+ TYPE_ICP_CONTROL_REGS)
-typedef struct ICPCtrlRegsState {
+struct ICPCtrlRegsState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq mmc_irq;
uint32_t intreg_state;
-} ICPCtrlRegsState;
+};
#define ICP_GPIO_MMC_WPROT "mmc-wprot"
#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
case 3: /* CP_DECODE */
return 0x11;
default:
- hw_error("icp_control_read: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
return 0;
}
}
/* Nothing interesting implemented yet. */
break;
default:
- hw_error("icp_control_write: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
}
}
static void integratorcp_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
DeviceState *dev, *sic, *icp;
+ DriveInfo *dinfo;
int i;
cpuobj = object_new(machine->cpu_type);
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
- object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
+ object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu = ARM_CPU(cpuobj);
- memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
- ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
- memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
/* And again at address 0x80000000 */
- memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
+ memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
+ 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
- dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
+ dev = qdev_new(TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
- qdev_connect_gpio_out(dev, 0,
+ qdev_connect_gpio_out_named(dev, "card-read-only", 0,
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
- qdev_connect_gpio_out(dev, 1,
+ qdev_connect_gpio_out_named(dev, "card-inserted", 0,
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
+ dinfo = drive_get_next(IF_SD);
+ if (dinfo) {
+ DeviceState *card;
+
+ card = qdev_new(TYPE_SD_CARD);
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
+ &error_fatal);
+ }
+
+ sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
if (nd_table[0].used)
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
integrator_binfo.ram_size = ram_size;
- integrator_binfo.kernel_filename = kernel_filename;
- integrator_binfo.kernel_cmdline = kernel_cmdline;
- integrator_binfo.initrd_filename = initrd_filename;
- arm_load_kernel(cpu, &integrator_binfo);
+ arm_load_kernel(cpu, machine, &integrator_binfo);
}
static void integratorcp_machine_init(MachineClass *mc)
mc->init = integratorcp_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ mc->default_ram_id = "integrator.ram";
}
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = core_properties;
+ device_class_set_props(dc, core_properties);
dc->realize = integratorcm_realize;
dc->vmsd = &vmstate_integratorcm;
}
projects / mirror_qemu.git / blobdiff