event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
}
- dev = qdev_create(NULL, TYPE_ACPI_GED);
+ dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
return;
}
- dev = qdev_create(NULL, itsclass);
+ dev = qdev_new(itsclass);
object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
fdt_add_its_gic_node(vms);
int irq = vms->irqmap[VIRT_GIC_V2M];
DeviceState *dev;
- dev = qdev_create(NULL, "arm-gicv2m");
+ dev = qdev_new("arm-gicv2m");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
- vms->gic = qdev_create(NULL, gictype);
+ vms->gic = qdev_new(gictype);
qdev_prop_set_uint32(vms->gic, "revision", type);
qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
/* Note that the num-irq property counts both internal and external
vms->virt);
}
}
- qdev_init_nofail(vms->gic);
gicbusdev = SYS_BUS_DEVICE(vms->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
if (type == 3) {
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
int irq = vms->irqmap[uart];
const char compat[] = "arm,pl011\0arm,primecell";
const char clocknames[] = "uartclk\0apb_pclk";
- DeviceState *dev = qdev_create(NULL, TYPE_PL011);
+ DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
* Create a single flash device. We use the same parameters as
* the flash devices on the Versatile Express board.
*/
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
qdev_prop_set_string(dev, "name", name);
- object_property_add_child(OBJECT(vms), name, OBJECT(dev),
- &error_abort);
+ object_property_add_child(OBJECT(vms), name, OBJECT(dev));
object_property_add_alias(OBJECT(vms), alias_prop_name,
- OBJECT(dev), "drive", &error_abort);
+ OBJECT(dev), "drive");
return PFLASH_CFI01(dev);
}
{
DeviceState *dev = DEVICE(flash);
- assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
+ assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
return;
}
- dev = qdev_create(NULL, "arm-smmuv3");
+ dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
int i, ecam_id;
PCIHostState *pci;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
base_ecam = vms->memmap[ecam_id].base;
int i;
MemoryRegion *sysmem = get_system_memory();
- dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
vms->platform_bus_dev = dev;
s = SYS_BUS_DEVICE(dev);
visit_type_OnOffAuto(v, name, &vms->acpi, errp);
}
+static bool virt_get_ras(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->ras;
+}
+
+static void virt_set_ras(Object *obj, bool value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->ras = value;
+}
+
static char *virt_get_gic_version(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
object_class_property_add(oc, "acpi", "OnOffAuto",
virt_get_acpi, virt_set_acpi,
- NULL, NULL, &error_abort);
+ NULL, NULL);
object_class_property_set_description(oc, "acpi",
- "Enable ACPI", &error_abort);
+ "Enable ACPI");
}
static void virt_instance_init(Object *obj)
*/
vms->secure = false;
object_property_add_bool(obj, "secure", virt_get_secure,
- virt_set_secure, NULL);
+ virt_set_secure);
object_property_set_description(obj, "secure",
"Set on/off to enable/disable the ARM "
- "Security Extensions (TrustZone)",
- NULL);
+ "Security Extensions (TrustZone)");
/* EL2 is also disabled by default, for similar reasons */
vms->virt = false;
object_property_add_bool(obj, "virtualization", virt_get_virt,
- virt_set_virt, NULL);
+ virt_set_virt);
object_property_set_description(obj, "virtualization",
"Set on/off to enable/disable emulating a "
"guest CPU which implements the ARM "
- "Virtualization Extensions",
- NULL);
+ "Virtualization Extensions");
/* High memory is enabled by default */
vms->highmem = true;
object_property_add_bool(obj, "highmem", virt_get_highmem,
- virt_set_highmem, NULL);
+ virt_set_highmem);
object_property_set_description(obj, "highmem",
"Set on/off to enable/disable using "
- "physical address space above 32 bits",
- NULL);
+ "physical address space above 32 bits");
vms->gic_version = VIRT_GIC_VERSION_NOSEL;
object_property_add_str(obj, "gic-version", virt_get_gic_version,
- virt_set_gic_version, NULL);
+ virt_set_gic_version);
object_property_set_description(obj, "gic-version",
"Set GIC version. "
- "Valid values are 2, 3, host and max",
- NULL);
+ "Valid values are 2, 3, host and max");
vms->highmem_ecam = !vmc->no_highmem_ecam;
/* Default allows ITS instantiation */
vms->its = true;
object_property_add_bool(obj, "its", virt_get_its,
- virt_set_its, NULL);
+ virt_set_its);
object_property_set_description(obj, "its",
"Set on/off to enable/disable "
- "ITS instantiation",
- NULL);
+ "ITS instantiation");
}
/* Default disallows iommu instantiation */
vms->iommu = VIRT_IOMMU_NONE;
- object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
+ object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu);
object_property_set_description(obj, "iommu",
"Set the IOMMU type. "
- "Valid values are none and smmuv3",
- NULL);
+ "Valid values are none and smmuv3");
+
+ /* Default disallows RAS instantiation */
+ vms->ras = false;
+ object_property_add_bool(obj, "ras", virt_get_ras,
+ virt_set_ras);
+ object_property_set_description(obj, "ras",
+ "Set on/off to enable/disable reporting host memory errors "
+ "to a KVM guest using ACPI and guest external abort exceptions");
vms->irqmap = a15irqmap;
projects / mirror_qemu.git / blobdiff