#include "ati_regs.h"
#include "vga_regs.h"
#include "qemu/log.h"
+#include "qemu/module.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "ui/console.h"
+#include "hw/display/i2c-ddc.h"
#include "trace.h"
#define ATI_DEBUG_HW_CURSOR 0
DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
+ s->vga.big_endian_fb = false;
/* reset VBE regs then set up mode */
s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
}
}
+static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base)
+{
+ bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1);
+ bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1);
+
+ bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c);
+ d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d);
+
+ data &= ~0xf00ULL;
+ if (c) {
+ data |= BIT(base + 9);
+ }
+ if (d) {
+ data |= BIT(base + 8);
+ }
+ return data;
+}
+
static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
unsigned int size)
{
case DAC_CNTL:
val = s->regs.dac_cntl;
break;
-/* case GPIO_MONID: FIXME hook up DDC I2C here */
+ case GPIO_VGA_DDC:
+ val = s->regs.gpio_vga_ddc;
+ break;
+ case GPIO_DVI_DDC:
+ val = s->regs.gpio_dvi_ddc;
+ break;
+ case GPIO_MONID ... GPIO_MONID + 3:
+ val = ati_reg_read_offs(s->regs.gpio_monid,
+ addr - GPIO_MONID, size);
+ break;
case PALETTE_INDEX:
/* FIXME unaligned access */
val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16;
break;
case DEFAULT_OFFSET:
val = s->regs.default_offset;
+ if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ val >>= 10;
+ val |= s->regs.default_pitch << 16;
+ val |= s->regs.default_tile << 30;
+ }
break;
case DEFAULT_PITCH:
val = s->regs.default_pitch;
+ val |= s->regs.default_tile << 16;
break;
case DEFAULT_SC_BOTTOM_RIGHT:
val = s->regs.default_sc_bottom_right;
s->regs.dac_cntl = data & 0xffffe3ff;
s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
break;
-/* case GPIO_MONID: FIXME hook up DDC I2C here */
+ case GPIO_VGA_DDC:
+ if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ /* FIXME: Maybe add a property to select VGA or DVI port? */
+ }
+ break;
+ case GPIO_DVI_DDC:
+ if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0);
+ }
+ break;
+ case GPIO_MONID ... GPIO_MONID + 3:
+ /* FIXME What does Radeon have here? */
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ ati_reg_write_offs(&s->regs.gpio_monid,
+ addr - GPIO_MONID, data, size);
+ /*
+ * Rage128p accesses DDC used to get EDID via these bits.
+ * Only touch i2c when write overlaps 3rd byte because some
+ * drivers access this reg via multiple partial writes and
+ * without this spurious bits would be sent.
+ */
+ if ((s->regs.gpio_monid & BIT(25)) &&
+ addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) {
+ s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1);
+ }
+ }
+ break;
case PALETTE_INDEX ... PALETTE_INDEX + 3:
if (size == 4) {
vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
break;
case SRC_PITCH_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
- s->regs.src_offset = (data & 0x1fffff) << 5;
- s->regs.src_pitch = (data >> 21) & 0x3ff;
+ s->regs.src_offset = (data & 0x1fffff) << 4;
+ s->regs.src_pitch = (data & 0x7fe00000) >> 21;
s->regs.src_tile = data >> 31;
} else {
- s->regs.src_offset = (data & 0x3fffff) << 11;
+ s->regs.src_offset = (data & 0x3fffff) << 10;
s->regs.src_pitch = (data & 0x3fc00000) >> 16;
s->regs.src_tile = (data >> 30) & 1;
}
break;
case DST_PITCH_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
- s->regs.dst_offset = (data & 0x1fffff) << 5;
- s->regs.dst_pitch = (data >> 21) & 0x3ff;
+ s->regs.dst_offset = (data & 0x1fffff) << 4;
+ s->regs.dst_pitch = (data & 0x7fe00000) >> 21;
s->regs.dst_tile = data >> 31;
} else {
- s->regs.dst_offset = (data & 0x3fffff) << 11;
+ s->regs.dst_offset = (data & 0x3fffff) << 10;
s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
s->regs.dst_tile = data >> 30;
}
s->regs.dp_write_mask = data;
break;
case DEFAULT_OFFSET:
- data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
- 0x03fffc00 : 0xfffffc00);
- s->regs.default_offset = data;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.default_offset = data & 0xfffffff0;
+ } else {
+ /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */
+ s->regs.default_offset = (data & 0x3fffff) << 10;
+ s->regs.default_pitch = (data & 0x3fc00000) >> 16;
+ s->regs.default_tile = data >> 30;
+ }
break;
case DEFAULT_PITCH:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
- s->regs.default_pitch = data & 0x103ff;
+ s->regs.default_pitch = data & 0x3fff;
+ s->regs.default_tile = (data >> 16) & 1;
}
break;
case DEFAULT_SC_BOTTOM_RIGHT:
vga->cursor_draw_line = ati_cursor_draw_line;
}
+ /* ddc, edid */
+ I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
+ bitbang_i2c_init(&s->bbi2c, i2cbus);
+ I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
+ i2c_set_slave_address(i2cddc, 0x50);
+
/* mmio register space */
memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
"ati.mmregs", 0x4000);
k->class_id = PCI_CLASS_DISPLAY_VGA;
k->vendor_id = PCI_VENDOR_ID_ATI;
k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF;
- k->romfile = "vgabios-stdvga.bin";
+ k->romfile = "vgabios-ati.bin";
k->realize = ati_vga_realize;
k->exit = ati_vga_exit;
}
projects / mirror_qemu.git / blobdiff