}
}
+static void virtio_vga_base_gl_flushed(void *opaque)
+{
+ VirtIOVGABase *vvga = opaque;
+ VirtIOGPUBase *g = vvga->vgpu;
+
+ if (g->hw_ops->gl_flushed) {
+ g->hw_ops->gl_flushed(g);
+ }
+}
+
+static int virtio_vga_base_get_flags(void *opaque)
+{
+ VirtIOVGABase *vvga = opaque;
+ VirtIOGPUBase *g = vvga->vgpu;
+
+ return g->hw_ops->get_flags(g);
+}
+
static const GraphicHwOps virtio_vga_base_ops = {
+ .get_flags = virtio_vga_base_get_flags,
.invalidate = virtio_vga_base_invalidate_display,
.gfx_update = virtio_vga_base_update_display,
.text_update = virtio_vga_base_text_update,
.ui_info = virtio_vga_base_ui_info,
.gl_block = virtio_vga_base_gl_block,
+ .gl_flushed = virtio_vga_base_gl_flushed,
};
static const VMStateDescription vmstate_virtio_vga_base = {
vga_dirty_log_start(&vvga->vga);
}
+static bool virtio_vga_get_big_endian_fb(Object *obj, Error **errp)
+{
+ VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
+
+ return d->vga.big_endian_fb;
+}
+
+static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
+{
+ VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
+
+ d->vga.big_endian_fb = value;
+}
+
static Property virtio_vga_base_properties[] = {
DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
DEFINE_PROP_END_OF_LIST(),
k->realize = virtio_vga_base_realize;
pcidev_k->romfile = "vgabios-virtio.bin";
pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
+
+ /* Expose framebuffer byteorder via QOM */
+ object_class_property_add_bool(klass, "big-endian-framebuffer",
+ virtio_vga_get_big_endian_fb,
+ virtio_vga_set_big_endian_fb);
}
static TypeInfo virtio_vga_base_info = {