* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "qemu-common.h"
+#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "qemu/timer.h"
#include "hw/arm/omap.h"
#include "hw/irq.h"
static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
{
- return s->intr_update(s);
+ s->intr_update(s);
}
static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
a->pck_element = 0;
if (unlikely(!ch->elements || !ch->frames)) {
- printf("%s: bad DMA request\n", __FUNCTION__);
+ printf("%s: bad DMA request\n", __func__);
return;
}
continue;
#endif
printf("%s: Bus time-out in DMA%i operation\n",
- __FUNCTION__, dma->num);
+ __func__, dma->num);
}
min_elems = INT_MAX;
ch->burst[0] = (value & 0x0180) >> 7;
ch->pack[0] = (value & 0x0040) >> 6;
ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
+ if (ch->port[0] >= __omap_dma_port_last) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n",
+ __func__, ch->port[0]);
+ }
+ if (ch->port[1] >= __omap_dma_port_last) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA port %i\n",
+ __func__, ch->port[1]);
+ }
ch->data_type = 1 << (value & 3);
- if (ch->port[0] >= __omap_dma_port_last)
- printf("%s: invalid DMA port %i\n", __FUNCTION__,
- ch->port[0]);
- if (ch->port[1] >= __omap_dma_port_last)
- printf("%s: invalid DMA port %i\n", __FUNCTION__,
- ch->port[1]);
- if ((value & 3) == 3)
- printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
+ if ((value & 3) == 3) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bad data_type for DMA channel\n", __func__);
+ ch->data_type >>= 1;
+ }
break;
case 0x02: /* SYS_DMA_CCR_CH0 */
case 0x480: /* DMA_PCh0_SR */
case 0x482: /* DMA_PCh1_SR */
case 0x4c0: /* DMA_PChD_SR_0 */
- printf("%s: Physical Channel Status Registers not implemented.\n",
- __FUNCTION__);
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Physical Channel Status Registers not implemented\n",
+ __func__);
*ret = 0xff;
break;
int reg, ch;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
enum omap_dma_model model)
{
int num_irqs, memsize, i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
if (model <= omap_dma_3_1) {
num_irqs = 6;
}
omap_dma_setcaps(s);
- omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
+ omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, 1);
struct omap_dma_channel_s *ch;
if (size == 1) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
if (value & 2) /* SOFTRESET */
omap_dma_reset(s->dma);
s->ocp = value & 0x3321;
- if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
- fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
+ if (((s->ocp >> 12) & 3) == 3) { /* MIDLEMODE */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid DMA power mode\n",
+ __func__);
+ }
return;
case 0x78: /* DMA4_GCR */
s->gcr = value & 0x00ff00ff;
- if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
- fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
+ if ((value & 0xff) == 0x00) { /* MAX_CHANNEL_FIFO_DEPTH */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: wrong FIFO depth in GCR\n",
+ __func__);
+ }
return;
case 0x80 ... 0xfff:
case 0x00: /* DMA4_CCR */
ch->buf_disable = (value >> 25) & 1;
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
- if (ch->buf_disable && !ch->src_sync)
- fprintf(stderr, "%s: Buffering disable is not allowed in "
- "destination synchronised mode\n", __FUNCTION__);
+ if (ch->buf_disable && !ch->src_sync) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Buffering disable is not allowed in "
+ "destination synchronised mode\n", __func__);
+ }
ch->prefetch = (value >> 23) & 1;
ch->bs = (value >> 18) & 1;
ch->transparent_copy = (value >> 17) & 1;
ch->suspend = (value & 0x0100) >> 8;
ch->priority = (value & 0x0040) >> 6;
ch->fs = (value & 0x0020) >> 5;
- if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
- fprintf(stderr, "%s: For a packet transfer at least one port "
- "must be constant-addressed\n", __FUNCTION__);
+ if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: For a packet transfer at least one port "
+ "must be constant-addressed\n", __func__);
+ }
ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
/* XXX must be 0x01 for CamDMA */
ch->endian_lock[0] =(value >> 20) & 1;
ch->endian[1] =(value >> 19) & 1;
ch->endian_lock[1] =(value >> 18) & 1;
- if (ch->endian[0] != ch->endian[1])
- fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
- __FUNCTION__);
+ if (ch->endian[0] != ch->endian[1]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: DMA endianness conversion enable attempt\n",
+ __func__);
+ }
ch->write_mode = (value >> 16) & 3;
ch->burst[1] = (value & 0xc000) >> 14;
ch->pack[1] = (value & 0x2000) >> 13;
ch->burst[0] = (value & 0x0180) >> 7;
ch->pack[0] = (value & 0x0040) >> 6;
ch->translate[0] = (value & 0x003c) >> 2;
- if (ch->translate[0] | ch->translate[1])
- fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
- __FUNCTION__);
+ if (ch->translate[0] | ch->translate[1]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bad MReqAddressTranslate sideband signal\n",
+ __func__);
+ }
ch->data_type = 1 << (value & 3);
- if ((value & 3) == 3)
- printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
+ if ((value & 3) == 3) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bad data_type for DMA channel\n", __func__);
+ ch->data_type >>= 1;
+ }
break;
case 0x14: /* DMA4_CEN */
int chans, omap_clk iclk, omap_clk fclk)
{
int i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
s->model = omap_dma_4;
s->chans = chans;
s->intr_update = omap_dma_interrupts_4_update;
omap_dma_setcaps(s);
- omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
+ omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, !!s->dma->freq);