/*
* QEMU i8255x (PRO100) emulation
*
- * Copyright (C) 2006-2010 Stefan Weil
+ * Copyright (C) 2006-2011 Stefan Weil
*
* Portions of the code are copies from grub / etherboot eepro100.c
* and linux e100.c.
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Tested features (i82559):
- * PXE boot (i386) ok
+ * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
* Linux networking (i386) ok
*
* Untested:
- * non-i386 platforms
* Windows networking
*
* References:
* * Wake-on-LAN is not implemented.
*/
-#include <stdbool.h> /* bool */
#include <stddef.h> /* offsetof */
#include "hw.h"
#include "pci.h"
#include "net.h"
#include "eeprom93xx.h"
+#include "sysemu.h"
+#include "dma.h"
+
+/* QEMU sends frames smaller than 60 bytes to ethernet nics.
+ * Such frames are rejected by real nics and their emulations.
+ * To avoid this behaviour, other nic emulations pad received
+ * frames. The following definition enables this padding for
+ * eepro100, too. We keep the define around in case it might
+ * become useful the future if the core networking is ever
+ * changed to pad short packets itself. */
+#define CONFIG_PAD_RECEIVED_FRAMES
#define KiB 1024
#define i82559C 0x82559c
#define i82559ER 0x82559e
#define i82562 0x82562
+#define i82801 0x82801
/* Use 64 word EEPROM. TODO: could be a runtime option. */
#define EEPROM_SIZE 64
#define INT_MASK 0x0100
#define DRVR_INT 0x0200 /* Driver generated interrupt. */
+typedef struct {
+ PCIDeviceInfo pci;
+ uint32_t device;
+ uint8_t stats_size;
+ bool has_extended_tcb_support;
+ bool power_management;
+} E100PCIDeviceInfo;
+
/* Offsets to the various registers.
All accesses need not be longword aligned. */
-enum speedo_offsets {
+typedef enum {
SCBStatus = 0, /* Status Word. */
SCBAck = 1,
SCBCmd = 2, /* Rx/Command Unit command and status. */
SCBpmdr = 27, /* Power Management Driver. */
SCBgctrl = 28, /* General Control. */
SCBgstat = 29, /* General Status. */
-};
+} E100RegisterOffset;
/* A speedo3 transmit buffer descriptor with two buffers... */
typedef struct {
uint32_t rx_buf_addr; /* void * */
uint16_t count;
uint16_t size;
- char packet[MAX_ETH_FRAME_SIZE + 4];
+ /* Ethernet frame data follows. */
} eepro100_rx_t;
typedef enum {
typedef struct {
PCIDevice dev;
- uint8_t mult[8]; /* multicast mask array */
- int mmio_index;
+ /* Hash register (multicast mask array, multiple individual addresses). */
+ uint8_t mult[8];
+ MemoryRegion mmio_bar;
+ MemoryRegion io_bar;
+ MemoryRegion flash_bar;
NICState *nic;
NICConf conf;
uint8_t scb_stat; /* SCB stat/ack byte */
uint8_t int_stat; /* PCI interrupt status */
/* region must not be saved by nic_save. */
- uint32_t region[3]; /* PCI region addresses */
uint16_t mdimem[32];
eeprom_t *eeprom;
uint32_t device; /* device variant */
- uint32_t pointer;
/* (cu_base + cu_offset) address the next command block in the command block list. */
uint32_t cu_base; /* CU base address */
uint32_t cu_offset; /* CU address offset */
/* Statistical counters. Also used for wake-up packet (i82559). */
eepro100_stats_t statistics;
-#if 0
- uint16_t status;
-#endif
+ /* Data in mem is always in the byte order of the controller (le).
+ * It must be dword aligned to allow direct access to 32 bit values. */
+ uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
/* Configuration bytes. */
uint8_t configuration[22];
- /* Data in mem is always in the byte order of the controller (le). */
- uint8_t mem[PCI_MEM_SIZE];
/* vmstate for each particular nic */
VMStateDescription *vmstate;
0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
-/* XXX: optimize */
-static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
-{
- val = cpu_to_le32(val);
- cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
-}
-
#define POLYNOMIAL 0x04c11db6
/* From FreeBSD */
return (crc & BITS(7, 2)) >> 2;
}
+/* Read a 16 bit control/status (CSR) register. */
+static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
+{
+ assert(!((uintptr_t)&s->mem[addr] & 1));
+ return le16_to_cpup((uint16_t *)&s->mem[addr]);
+}
+
+/* Read a 32 bit control/status (CSR) register. */
+static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
+{
+ assert(!((uintptr_t)&s->mem[addr] & 3));
+ return le32_to_cpup((uint32_t *)&s->mem[addr]);
+}
+
+/* Write a 16 bit control/status (CSR) register. */
+static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
+ uint16_t val)
+{
+ assert(!((uintptr_t)&s->mem[addr] & 1));
+ cpu_to_le16w((uint16_t *)&s->mem[addr], val);
+}
+
+/* Read a 32 bit control/status (CSR) register. */
+static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
+ uint32_t val)
+{
+ assert(!((uintptr_t)&s->mem[addr] & 3));
+ cpu_to_le32w((uint32_t *)&s->mem[addr], val);
+}
+
#if defined(DEBUG_EEPRO100)
static const char *nic_dump(const uint8_t * buf, unsigned size)
{
}
#endif
-static void pci_reset(EEPRO100State * s)
+static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
{
uint32_t device = s->device;
uint8_t *pci_conf = s->dev.config;
- bool power_management = 1;
TRACE(OTHER, logout("%p\n", s));
- /* PCI Vendor ID */
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- /* PCI Device ID depends on device and is set below. */
/* PCI Status */
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
- /* PCI Revision ID */
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
- pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
+ pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
+ PCI_STATUS_FAST_BACK);
/* PCI Latency Timer */
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
- /* Capability Pointer */
- /* TODO: revisions with power_management 1 use this but
- * do not set new capability list bit in status register. */
- pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0xdc);
+ /* Capability Pointer is set by PCI framework. */
+ /* Interrupt Line */
+ /* Interrupt Pin */
+ pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
/* Minimum Grant */
pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
/* Maximum Latency */
pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
+ s->stats_size = e100_device->stats_size;
+ s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
+
switch (device) {
case i82550:
- /* TODO: check device id. */
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
- /* Revision ID: 0x0c, 0x0d, 0x0e. */
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
- /* TODO: check size of statistical counters. */
- s->stats_size = 80;
- /* TODO: check extended tcb support. */
- s->has_extended_tcb_support = 1;
- break;
case i82551:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
- /* Revision ID: 0x0f, 0x10. */
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0f);
- /* TODO: check size of statistical counters. */
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
- break;
case i82557A:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x01);
- pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
- power_management = 0;
- break;
case i82557B:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x02);
- pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
- power_management = 0;
- break;
case i82557C:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x03);
- pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
- power_management = 0;
- break;
case i82558A:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x04);
- s->stats_size = 76;
- s->has_extended_tcb_support = 1;
- break;
case i82558B:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x05);
- s->stats_size = 76;
- s->has_extended_tcb_support = 1;
- break;
case i82559A:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x06);
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
- break;
case i82559B:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x07);
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
- break;
- case i82559C:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
- /* TODO: Windows wants revision id 0x0c. */
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0c);
-#if EEPROM_SIZE > 0
- pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
- pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
-#endif
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
- break;
case i82559ER:
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
- pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
- PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x09);
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
- break;
case i82562:
- /* TODO: check device id. */
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
- /* TODO: wrong revision id. */
- pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
- s->stats_size = 80;
- s->has_extended_tcb_support = 1;
+ case i82801:
+ case i82559C:
break;
default:
logout("Device %X is undefined!\n", device);
}
+ /* Standard TxCB. */
+ s->configuration[6] |= BIT(4);
+
+ /* Standard statistical counters. */
s->configuration[6] |= BIT(5);
if (s->stats_size == 80) {
}
assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
- if (power_management) {
+ if (e100_device->power_management) {
/* Power Management Capabilities */
- pci_set_byte(pci_conf + 0xdc, 0x01);
- /* Next Item Pointer */
- /* Capability ID */
- pci_set_word(pci_conf + 0xde, 0x7e21);
+ int cfg_offset = 0xdc;
+ int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
+ cfg_offset, PCI_PM_SIZEOF);
+ assert(r >= 0);
+ pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
+#if 0 /* TODO: replace dummy code for power management emulation. */
/* TODO: Power Management Control / Status. */
+ pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
+ pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
+#endif
}
#if EEPROM_SIZE > 0
TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
memset(s->mem, 0, sizeof(s->mem));
- uint32_t val = BIT(21);
- memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
+ e100_write_reg4(s, SCBCtrlMDI, BIT(21));
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
{
EEPRO100State *s = opaque;
TRACE(OTHER, logout("%p\n", s));
- /* TODO: Clearing of multicast table for selective reset, too? */
+ /* TODO: Clearing of hash register for selective reset, too? */
memset(&s->mult[0], 0, sizeof(s->mult));
nic_selective_reset(s);
}
}
#endif /* DEBUG_EEPRO100 */
-#if 0
-static uint16_t eepro100_read_status(EEPRO100State * s)
-{
- uint16_t val = s->status;
- TRACE(OTHER, logout("val=0x%04x\n", val));
- return val;
-}
-
-static void eepro100_write_status(EEPRO100State * s, uint16_t val)
-{
- TRACE(OTHER, logout("val=0x%04x\n", val));
- s->status = val;
-}
-#endif
-
/*****************************************************************************
*
* Command emulation.
* values which really matter.
* Number of data should check configuration!!!
*/
- cpu_physical_memory_write(s->statsaddr,
- (uint8_t *) & s->statistics, s->stats_size);
- stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
- stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
- stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
- stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
+ pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
+ stl_le_pci_dma(&s->dev, s->statsaddr + 0,
+ s->statistics.tx_good_frames);
+ stl_le_pci_dma(&s->dev, s->statsaddr + 36,
+ s->statistics.rx_good_frames);
+ stl_le_pci_dma(&s->dev, s->statsaddr + 48,
+ s->statistics.rx_resource_errors);
+ stl_le_pci_dma(&s->dev, s->statsaddr + 60,
+ s->statistics.rx_short_frame_errors);
#if 0
- stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
- stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
+ stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
+ stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
missing("CU dump statistical counters");
#endif
}
static void read_cb(EEPRO100State *s)
{
- cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
+ pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
s->tx.status = le16_to_cpu(s->tx.status);
s->tx.command = le16_to_cpu(s->tx.command);
s->tx.link = le32_to_cpu(s->tx.link);
}
assert(tcb_bytes <= sizeof(buf));
while (size < tcb_bytes) {
- uint32_t tx_buffer_address = ldl_phys(tbd_address);
- uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
+ uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
+ uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
#if 0
- uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
+ uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
#endif
tbd_address += 8;
TRACE(RXTX, logout
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
tx_buffer_address, tx_buffer_size));
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
- cpu_physical_memory_read(tx_buffer_address, &buf[size],
- tx_buffer_size);
+ pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
size += tx_buffer_size;
}
if (tbd_array == 0xffffffff) {
if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
/* Extended Flexible TCB. */
for (; tbd_count < 2; tbd_count++) {
- uint32_t tx_buffer_address = ldl_phys(tbd_address);
- uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
- uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
+ uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
+ tbd_address);
+ uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
+ tbd_address + 4);
+ uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
+ tbd_address + 6);
tbd_address += 8;
TRACE(RXTX, logout
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
tx_buffer_address, tx_buffer_size));
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
- cpu_physical_memory_read(tx_buffer_address, &buf[size],
- tx_buffer_size);
+ pci_dma_read(&s->dev, tx_buffer_address,
+ &buf[size], tx_buffer_size);
size += tx_buffer_size;
if (tx_buffer_el & 1) {
break;
}
tbd_address = tbd_array;
for (; tbd_count < s->tx.tbd_count; tbd_count++) {
- uint32_t tx_buffer_address = ldl_phys(tbd_address);
- uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
- uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
+ uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
+ uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
+ uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
tbd_address += 8;
TRACE(RXTX, logout
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
tx_buffer_address, tx_buffer_size));
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
- cpu_physical_memory_read(tx_buffer_address, &buf[size],
- tx_buffer_size);
+ pci_dma_read(&s->dev, tx_buffer_address,
+ &buf[size], tx_buffer_size);
size += tx_buffer_size;
if (tx_buffer_el & 1) {
break;
TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
for (i = 0; i < multicast_count; i += 6) {
uint8_t multicast_addr[6];
- cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
+ pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
unsigned mcast_idx = compute_mcast_idx(multicast_addr);
assert(mcast_idx < 64);
bool bit_s;
bool bit_i;
bool bit_nc;
- bool success = true;
+ uint16_t ok_status = STATUS_OK;
s->cb_address = s->cu_base + s->cu_offset;
read_cb(s);
bit_el = ((s->tx.command & COMMAND_EL) != 0);
/* Do nothing. */
break;
case CmdIASetup:
- cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
+ pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
break;
case CmdConfigure:
- cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
- sizeof(s->configuration));
- TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
+ pci_dma_read(&s->dev, s->cb_address + 8,
+ &s->configuration[0], sizeof(s->configuration));
+ TRACE(OTHER, logout("configuration: %s\n",
+ nic_dump(&s->configuration[0], 16)));
+ TRACE(OTHER, logout("configuration: %s\n",
+ nic_dump(&s->configuration[16],
+ ARRAY_SIZE(s->configuration) - 16)));
+ if (s->configuration[20] & BIT(6)) {
+ TRACE(OTHER, logout("Multiple IA bit\n"));
+ }
break;
case CmdMulticastList:
set_multicast_list(s);
case CmdTx:
if (bit_nc) {
missing("CmdTx: NC = 0");
- success = false;
+ ok_status = 0;
break;
}
tx_command(s);
break;
default:
missing("undefined command");
- success = false;
+ ok_status = 0;
break;
}
/* Write new status. */
- stw_phys(s->cb_address, s->tx.status | STATUS_C | (success ? STATUS_OK : 0));
+ stw_le_pci_dma(&s->dev, s->cb_address,
+ s->tx.status | ok_status | STATUS_C);
if (bit_i) {
/* CU completed action. */
eepro100_cx_interrupt(s);
logout("unexpected CU state is %u\n", cu_state);
}
set_cu_state(s, cu_active);
- s->cu_offset = s->pointer;
+ s->cu_offset = e100_read_reg4(s, SCBPointer);
action_command(s);
break;
case CU_RESUME:
break;
case CU_STATSADDR:
/* Load dump counters address. */
- s->statsaddr = s->pointer;
- TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
+ s->statsaddr = e100_read_reg4(s, SCBPointer);
+ TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
+ if (s->statsaddr & 3) {
+ /* Memory must be Dword aligned. */
+ logout("unaligned dump counters address\n");
+ /* Handling of misaligned addresses is undefined.
+ * Here we align the address by ignoring the lower bits. */
+ /* TODO: Test unaligned dump counter address on real hardware. */
+ s->statsaddr &= ~3;
+ }
break;
case CU_SHOWSTATS:
/* Dump statistical counters. */
TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
dump_statistics(s);
- stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
+ stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
break;
case CU_CMD_BASE:
/* Load CU base. */
TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
- s->cu_base = s->pointer;
+ s->cu_base = e100_read_reg4(s, SCBPointer);
break;
case CU_DUMPSTATS:
/* Dump and reset statistical counters. */
TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
dump_statistics(s);
- stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
+ stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
memset(&s->statistics, 0, sizeof(s->statistics));
break;
case CU_SRESUME:
#endif
}
set_ru_state(s, ru_ready);
- s->ru_offset = s->pointer;
+ s->ru_offset = e100_read_reg4(s, SCBPointer);
TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
break;
case RX_RESUME:
case RX_ADDR_LOAD:
/* Load RU base. */
TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
- s->ru_base = s->pointer;
+ s->ru_base = e100_read_reg4(s, SCBPointer);
break;
default:
logout("val=0x%02x (undefined RU command)\n", val);
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
{
- uint16_t val;
- memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
+ uint16_t val = e100_read_reg2(s, SCBeeprom);
if (eeprom93xx_read(s->eeprom)) {
val |= EEPROM_DO;
} else {
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
- /* mask unwriteable bits */
+ /* mask unwritable bits */
#if 0
val = SET_MASKED(val, 0x31, eeprom->value);
#endif
eeprom93xx_write(eeprom, eecs, eesk, eedi);
}
-static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
-{
- s->pointer = le32_to_cpu(val);
- TRACE(OTHER, logout("val=0x%08x\n", val));
-}
-
/*****************************************************************************
*
* MDI emulation.
static uint32_t eepro100_read_mdi(EEPRO100State * s)
{
- uint32_t val;
- memcpy(&val, &s->mem[0x10], sizeof(val));
+ uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
#ifdef DEBUG_EEPRO100
uint8_t raiseint = (val & BIT(29)) >> 29;
return val;
}
-static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
+static void eepro100_write_mdi(EEPRO100State *s)
{
+ uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
uint8_t raiseint = (val & BIT(29)) >> 29;
uint8_t opcode = (val & BITS(27, 26)) >> 26;
uint8_t phy = (val & BITS(25, 21)) >> 21;
}
}
val = (val & 0xffff0000) + data;
- memcpy(&s->mem[0x10], &val, sizeof(val));
+ e100_write_reg4(s, SCBCtrlMDI, val);
}
/*****************************************************************************
return 0;
}
-static void eepro100_write_port(EEPRO100State * s, uint32_t val)
+static void eepro100_write_port(EEPRO100State *s)
{
- val = le32_to_cpu(val);
+ uint32_t val = e100_read_reg4(s, SCBPort);
uint32_t address = (val & ~PORT_SELECTION_MASK);
uint8_t selection = (val & PORT_SELECTION_MASK);
switch (selection) {
case PORT_SELFTEST:
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
eepro100_selftest_t data;
- cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
+ pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
data.st_sign = 0xffffffff;
data.st_result = 0;
- cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
+ pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
break;
case PORT_SELECTIVE_RESET:
TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
{
- uint8_t val;
+ uint8_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&val, &s->mem[addr], sizeof(val));
+ val = s->mem[addr];
}
switch (addr) {
case SCBStatus:
-#if 0
- val = eepro100_read_status(s);
-#endif
- TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
- break;
case SCBAck:
-#if 0
- val = eepro100_read_status(s);
-#endif
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
case SCBCmd:
case SCBeeprom:
val = eepro100_read_eeprom(s);
break;
+ case SCBCtrlMDI:
+ case SCBCtrlMDI + 1:
+ case SCBCtrlMDI + 2:
+ case SCBCtrlMDI + 3:
+ val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ break;
case SCBpmdr: /* Power Management Driver Register */
val = 0;
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
+ case SCBgctrl: /* General Control Register */
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ break;
case SCBgstat: /* General Status Register */
/* 100 Mbps full duplex, valid link */
val = 0x07;
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
{
- uint16_t val;
+ uint16_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&val, &s->mem[addr], sizeof(val));
+ val = e100_read_reg2(s, addr);
}
switch (addr) {
case SCBStatus:
-#if 0
- val = eepro100_read_status(s);
-#endif
case SCBCmd:
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
break;
val = eepro100_read_eeprom(s);
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
break;
+ case SCBCtrlMDI:
+ case SCBCtrlMDI + 2:
+ val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ break;
default:
logout("addr=%s val=0x%04x\n", regname(addr), val);
missing("unknown word read");
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
{
- uint32_t val;
+ uint32_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&val, &s->mem[addr], sizeof(val));
+ val = e100_read_reg4(s, addr);
}
switch (addr) {
case SCBStatus:
-#if 0
- val = eepro100_read_status(s);
-#endif
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
break;
case SCBPointer:
-#if 0
- val = eepro100_read_pointer(s);
-#endif
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
break;
case SCBPort:
val = eepro100_read_port(s);
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
break;
+ case SCBflash:
+ val = eepro100_read_eeprom(s);
+ TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
+ break;
case SCBCtrlMDI:
val = eepro100_read_mdi(s);
break;
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
{
- if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&s->mem[addr], &val, sizeof(val));
+ /* SCBStatus is readonly. */
+ if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
+ s->mem[addr] = val;
}
- TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
-
switch (addr) {
case SCBStatus:
-#if 0
- eepro100_write_status(s, val);
-#endif
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
case SCBAck:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
eepro100_acknowledge(s);
break;
case SCBCmd:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
eepro100_write_command(s, val);
break;
case SCBIntmask:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
if (val & BIT(1)) {
eepro100_swi_interrupt(s);
}
eepro100_interrupt(s, 0);
break;
+ case SCBPointer:
+ case SCBPointer + 1:
+ case SCBPointer + 2:
+ case SCBPointer + 3:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ break;
+ case SCBPort:
+ case SCBPort + 1:
+ case SCBPort + 2:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ break;
case SCBPort + 3:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ eepro100_write_port(s);
+ break;
case SCBFlow: /* does not exist on 82557 */
case SCBFlow + 1:
case SCBFlow + 2:
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
break;
case SCBeeprom:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
eepro100_write_eeprom(s->eeprom, val);
break;
+ case SCBCtrlMDI:
+ case SCBCtrlMDI + 1:
+ case SCBCtrlMDI + 2:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ break;
+ case SCBCtrlMDI + 3:
+ TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
+ eepro100_write_mdi(s);
+ break;
default:
logout("addr=%s val=0x%02x\n", regname(addr), val);
missing("unknown byte write");
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
{
- if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&s->mem[addr], &val, sizeof(val));
+ /* SCBStatus is readonly. */
+ if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
+ e100_write_reg2(s, addr, val);
}
- TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
-
switch (addr) {
case SCBStatus:
-#if 0
- eepro100_write_status(s, val);
-#endif
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ s->mem[SCBAck] = (val >> 8);
eepro100_acknowledge(s);
break;
case SCBCmd:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
eepro100_write_command(s, val);
eepro100_write1(s, SCBIntmask, val >> 8);
break;
+ case SCBPointer:
+ case SCBPointer + 2:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ break;
+ case SCBPort:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ break;
+ case SCBPort + 2:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ eepro100_write_port(s);
+ break;
case SCBeeprom:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
eepro100_write_eeprom(s->eeprom, val);
break;
+ case SCBCtrlMDI:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ break;
+ case SCBCtrlMDI + 2:
+ TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
+ eepro100_write_mdi(s);
+ break;
default:
logout("addr=%s val=0x%04x\n", regname(addr), val);
missing("unknown word write");
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
{
if (addr <= sizeof(s->mem) - sizeof(val)) {
- memcpy(&s->mem[addr], &val, sizeof(val));
+ e100_write_reg4(s, addr, val);
}
switch (addr) {
case SCBPointer:
- eepro100_write_pointer(s, val);
+ TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
break;
case SCBPort:
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
- eepro100_write_port(s, val);
+ eepro100_write_port(s);
+ break;
+ case SCBflash:
+ TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
+ val = val >> 16;
+ eepro100_write_eeprom(s->eeprom, val);
break;
case SCBCtrlMDI:
- eepro100_write_mdi(s, val);
+ TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
+ eepro100_write_mdi(s);
break;
default:
logout("addr=%s val=0x%08x\n", regname(addr), val);
}
}
-/*****************************************************************************
- *
- * Port mapped I/O.
- *
- ****************************************************************************/
-
-static uint32_t ioport_read1(void *opaque, uint32_t addr)
+static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s\n", regname(addr));
-#endif
- return eepro100_read1(s, addr - s->region[1]);
-}
-
-static uint32_t ioport_read2(void *opaque, uint32_t addr)
-{
- EEPRO100State *s = opaque;
- return eepro100_read2(s, addr - s->region[1]);
-}
-
-static uint32_t ioport_read4(void *opaque, uint32_t addr)
-{
- EEPRO100State *s = opaque;
- return eepro100_read4(s, addr - s->region[1]);
-}
-
-static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
- eepro100_write1(s, addr - s->region[1], val);
-}
-
-static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
- eepro100_write2(s, addr - s->region[1], val);
-}
-
-static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
- eepro100_write4(s, addr - s->region[1], val);
-}
-
-/***********************************************************/
-/* PCI EEPRO100 definitions */
-
-static void pci_map(PCIDevice * pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
-
- TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
- "size=0x%08"FMT_PCIBUS", type=%d\n",
- region_num, addr, size, type));
-
- assert(region_num == 1);
- register_ioport_write(addr, size, 1, ioport_write1, s);
- register_ioport_read(addr, size, 1, ioport_read1, s);
- register_ioport_write(addr, size, 2, ioport_write2, s);
- register_ioport_read(addr, size, 2, ioport_read2, s);
- register_ioport_write(addr, size, 4, ioport_write4, s);
- register_ioport_read(addr, size, 4, ioport_read4, s);
-
- s->region[region_num] = addr;
-}
-/*****************************************************************************
- *
- * Memory mapped I/O.
- *
- ****************************************************************************/
-
-static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
- eepro100_write1(s, addr, val);
-}
-
-static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
- eepro100_write2(s, addr, val);
-}
-
-static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s val=0x%02x\n", regname(addr), val);
-#endif
- eepro100_write4(s, addr, val);
-}
-
-static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s\n", regname(addr));
-#endif
- return eepro100_read1(s, addr);
+ switch (size) {
+ case 1: return eepro100_read1(s, addr);
+ case 2: return eepro100_read2(s, addr);
+ case 4: return eepro100_read4(s, addr);
+ default: abort();
+ }
}
-static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void eepro100_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s\n", regname(addr));
-#endif
- return eepro100_read2(s, addr);
-}
-static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
-{
- EEPRO100State *s = opaque;
-#if 0
- logout("addr=%s\n", regname(addr));
-#endif
- return eepro100_read4(s, addr);
+ switch (size) {
+ case 1: return eepro100_write1(s, addr, data);
+ case 2: return eepro100_write2(s, addr, data);
+ case 4: return eepro100_write4(s, addr, data);
+ default: abort();
+ }
}
-static CPUWriteMemoryFunc * const pci_mmio_write[] = {
- pci_mmio_writeb,
- pci_mmio_writew,
- pci_mmio_writel
-};
-
-static CPUReadMemoryFunc * const pci_mmio_read[] = {
- pci_mmio_readb,
- pci_mmio_readw,
- pci_mmio_readl
+static const MemoryRegionOps eepro100_ops = {
+ .read = eepro100_read,
+ .write = eepro100_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
-static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
-
- TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
- "size=0x%08"FMT_PCIBUS", type=%d\n",
- region_num, addr, size, type));
-
- if (region_num == 0) {
- /* Map control / status registers. */
- cpu_register_physical_memory(addr, size, s->mmio_index);
- s->region[region_num] = addr;
- }
-}
-
static int nic_can_receive(VLANClientState *nc)
{
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
*/
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
uint16_t rfd_status = 0xa000;
+#if defined(CONFIG_PAD_RECEIVED_FRAMES)
+ uint8_t min_buf[60];
+#endif
static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
- /* TODO: check multiple IA bit. */
- if (s->configuration[20] & BIT(6)) {
- missing("Multiple IA bit");
- return -1;
+#if defined(CONFIG_PAD_RECEIVED_FRAMES)
+ /* Pad to minimum Ethernet frame length */
+ if (size < sizeof(min_buf)) {
+ memcpy(min_buf, buf, size);
+ memset(&min_buf[size], 0, sizeof(min_buf) - size);
+ buf = min_buf;
+ size = sizeof(min_buf);
}
+#endif
if (s->configuration[8] & 0x80) {
/* CSMA is disabled. */
logout("%p received while CSMA is disabled\n", s);
return -1;
+#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
} else if (size < 64 && (s->configuration[7] & BIT(0))) {
/* Short frame and configuration byte 7/0 (discard short receive) set:
* Short frame is discarded */
logout("%p received short frame (%zu byte)\n", s, size);
s->statistics.rx_short_frame_errors++;
-#if 0
return -1;
#endif
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
/* Promiscuous: receive all. */
TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
rfd_status |= 0x0004;
+ } else if (s->configuration[20] & BIT(6)) {
+ /* Multiple IA bit set. */
+ unsigned mcast_idx = compute_mcast_idx(buf);
+ assert(mcast_idx < 64);
+ if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
+ TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
+ } else {
+ TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
+ return -1;
+ }
} else {
TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
nic_dump(buf, size)));
}
/* !!! */
eepro100_rx_t rx;
- cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
- offsetof(eepro100_rx_t, packet));
+ pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
+ &rx, sizeof(eepro100_rx_t));
uint16_t rfd_command = le16_to_cpu(rx.command);
uint16_t rfd_size = le16_to_cpu(rx.size);
"(%zu bytes); data truncated\n", rfd_size, size);
size = rfd_size;
}
+#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
if (size < 64) {
rfd_status |= 0x0080;
}
+#endif
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
- stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
- rfd_status);
- stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
+ stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
+ offsetof(eepro100_rx_t, status), rfd_status);
+ stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
+ offsetof(eepro100_rx_t, count), size);
/* Early receive interrupt not supported. */
#if 0
eepro100_er_interrupt(s);
#if 0
assert(!(s->configuration[17] & BIT(0)));
#endif
- cpu_physical_memory_write(s->ru_base + s->ru_offset +
- offsetof(eepro100_rx_t, packet), buf, size);
+ pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
+ sizeof(eepro100_rx_t), buf, size);
s->statistics.rx_good_frames++;
eepro100_fr_interrupt(s);
s->ru_offset = le32_to_cpu(rx.link);
/* The eeprom should be saved and restored by its own routines. */
VMSTATE_UINT32(device, EEPRO100State),
/* TODO check device. */
- VMSTATE_UINT32(pointer, EEPRO100State),
VMSTATE_UINT32(cu_base, EEPRO100State),
VMSTATE_UINT32(cu_offset, EEPRO100State),
VMSTATE_UINT32(ru_base, EEPRO100State),
VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
-#if 0
- VMSTATE_UINT16(status, EEPRO100State),
-#endif
/* Configuration bytes. */
VMSTATE_BUFFER(configuration, EEPRO100State),
VMSTATE_END_OF_LIST()
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
- cpu_unregister_io_memory(s->mmio_index);
- vmstate_unregister(s->vmstate, s);
- eeprom93xx_free(s->eeprom);
+ memory_region_destroy(&s->mmio_bar);
+ memory_region_destroy(&s->io_bar);
+ memory_region_destroy(&s->flash_bar);
+ vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
+ eeprom93xx_free(&pci_dev->qdev, s->eeprom);
qemu_del_vlan_client(&s->nic->nc);
return 0;
}
.cleanup = nic_cleanup,
};
-static int nic_init(PCIDevice *pci_dev, uint32_t device)
+static int e100_nic_init(PCIDevice *pci_dev)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
+ E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
+ qdev_get_info(&pci_dev->qdev));
TRACE(OTHER, logout("\n"));
- s->device = device;
+ s->device = e100_device->device;
- pci_reset(s);
+ e100_pci_reset(s, e100_device);
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
* i82559 and later support 64 or 256 word EEPROM. */
- s->eeprom = eeprom93xx_new(EEPROM_SIZE);
+ s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
/* Handler for memory-mapped I/O */
- s->mmio_index =
- cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
-
- pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
- PCI_BASE_ADDRESS_SPACE_MEMORY |
- PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
- pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
- pci_map);
- pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
- pci_mmio_map);
+ memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
+ PCI_MEM_SIZE);
+ pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
+ memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
+ PCI_IO_SIZE);
+ pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
+ /* FIXME: flash aliases to mmio?! */
+ memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
+ PCI_FLASH_SIZE);
+ pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
- assert(s->region[1] == 0);
nic_reset(s);
s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
- pci_dev->qdev.info->name, pci_dev->qdev.id, s);
+ object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
qemu_register_reset(nic_reset, s);
- s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
+ s->vmstate = g_malloc(sizeof(vmstate_eepro100));
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
s->vmstate->name = s->nic->nc.model;
- vmstate_register(-1, s->vmstate, s);
-
- return 0;
-}
-
-static int pci_i82550_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82550);
-}
-
-static int pci_i82551_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82551);
-}
-
-static int pci_i82557a_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82557A);
-}
+ vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
-static int pci_i82557b_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82557B);
-}
+ add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
-static int pci_i82557c_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82557C);
-}
-
-static int pci_i82558a_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82558A);
-}
-
-static int pci_i82558b_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82558B);
-}
-
-static int pci_i82559a_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82559A);
-}
-
-static int pci_i82559b_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82559B);
-}
-
-static int pci_i82559c_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82559C);
-}
-
-static int pci_i82559er_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82559ER);
-}
-
-static int pci_i82562_init(PCIDevice *pci_dev)
-{
- return nic_init(pci_dev, i82562);
+ return 0;
}
-static PCIDeviceInfo eepro100_info[] = {
+static E100PCIDeviceInfo e100_devices[] = {
{
- .qdev.name = "i82550",
- .qdev.desc = "Intel i82550 Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82550_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861209.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82550",
+ .pci.qdev.desc = "Intel i82550 Ethernet",
+ .device = i82550,
+ /* TODO: check device id. */
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+ /* Revision ID: 0x0c, 0x0d, 0x0e. */
+ .pci.revision = 0x0e,
+ /* TODO: check size of statistical counters. */
+ .stats_size = 80,
+ /* TODO: check extended tcb support. */
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82551",
- .qdev.desc = "Intel i82551 Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82551_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861209.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82551",
+ .pci.qdev.desc = "Intel i82551 Ethernet",
+ .device = i82551,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+ /* Revision ID: 0x0f, 0x10. */
+ .pci.revision = 0x0f,
+ /* TODO: check size of statistical counters. */
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82557a",
- .qdev.desc = "Intel i82557A Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82557a_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82557a",
+ .pci.qdev.desc = "Intel i82557A Ethernet",
+ .device = i82557A,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x01,
+ .power_management = false,
},{
- .qdev.name = "i82557b",
- .qdev.desc = "Intel i82557B Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82557b_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82557b",
+ .pci.qdev.desc = "Intel i82557B Ethernet",
+ .device = i82557B,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x02,
+ .power_management = false,
},{
- .qdev.name = "i82557c",
- .qdev.desc = "Intel i82557C Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82557c_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82557c",
+ .pci.qdev.desc = "Intel i82557C Ethernet",
+ .device = i82557C,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x03,
+ .power_management = false,
},{
- .qdev.name = "i82558a",
- .qdev.desc = "Intel i82558A Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82558a_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82558a",
+ .pci.qdev.desc = "Intel i82558A Ethernet",
+ .device = i82558A,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x04,
+ .stats_size = 76,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82558b",
- .qdev.desc = "Intel i82558B Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82558b_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82558b",
+ .pci.qdev.desc = "Intel i82558B Ethernet",
+ .device = i82558B,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x05,
+ .stats_size = 76,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82559a",
- .qdev.desc = "Intel i82559A Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82559a_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82559a",
+ .pci.qdev.desc = "Intel i82559A Ethernet",
+ .device = i82559A,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x06,
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82559b",
- .qdev.desc = "Intel i82559B Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82559b_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82559b",
+ .pci.qdev.desc = "Intel i82559B Ethernet",
+ .device = i82559B,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+ .pci.revision = 0x07,
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82559c",
- .qdev.desc = "Intel i82559C Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82559c_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861229.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82559c",
+ .pci.qdev.desc = "Intel i82559C Ethernet",
+ .device = i82559C,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+#if 0
+ .pci.revision = 0x08,
+#endif
+ /* TODO: Windows wants revision id 0x0c. */
+ .pci.revision = 0x0c,
+#if EEPROM_SIZE > 0
+ .pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
+ .pci.subsystem_id = 0x0040,
+#endif
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82559er",
- .qdev.desc = "Intel i82559ER Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82559er_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861209.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82559er",
+ .pci.qdev.desc = "Intel i82559ER Ethernet",
+ .device = i82559ER,
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+ .pci.revision = 0x09,
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- .qdev.name = "i82562",
- .qdev.desc = "Intel i82562 Ethernet",
- .qdev.size = sizeof(EEPRO100State),
- .init = pci_i82562_init,
- .exit = pci_nic_uninit,
- .romfile = "gpxe-eepro100-80861209.rom",
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
- DEFINE_PROP_END_OF_LIST(),
- },
+ .pci.qdev.name = "i82562",
+ .pci.qdev.desc = "Intel i82562 Ethernet",
+ .device = i82562,
+ /* TODO: check device id. */
+ .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+ /* TODO: wrong revision id. */
+ .pci.revision = 0x0e,
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
},{
- /* end of list */
+ /* Toshiba Tecra 8200. */
+ .pci.qdev.name = "i82801",
+ .pci.qdev.desc = "Intel i82801 Ethernet",
+ .device = i82801,
+ .pci.device_id = 0x2449,
+ .pci.revision = 0x03,
+ .stats_size = 80,
+ .has_extended_tcb_support = true,
+ .power_management = true,
}
};
+static Property e100_properties[] = {
+ DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void eepro100_register_devices(void)
{
- pci_qdev_register_many(eepro100_info);
+ size_t i;
+ for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
+ PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
+ /* We use the same rom file for all device ids.
+ QEMU fixes the device id during rom load. */
+ pci_dev->vendor_id = PCI_VENDOR_ID_INTEL;
+ pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET;
+ pci_dev->romfile = "pxe-eepro100.rom";
+ pci_dev->init = e100_nic_init;
+ pci_dev->exit = pci_nic_uninit;
+ pci_dev->qdev.props = e100_properties;
+ pci_dev->qdev.size = sizeof(EEPRO100State);
+ pci_qdev_register(pci_dev);
+ }
}
device_init(eepro100_register_devices)
projects / mirror_qemu.git / blobdiff