#include "hw/acpi/vmgenid.h"
#include "sysemu/tpm_backend.h"
#include "hw/timer/mc146818rtc_regs.h"
+#include "hw/mem/memory-device.h"
#include "sysemu/numa.h"
/* Supported chipsets: */
} else {
pm->s3_disabled = false;
}
- qobject_decref(o);
+ qobject_unref(o);
o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
if (o) {
pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
} else {
pm->s4_disabled = false;
}
- qobject_decref(o);
+ qobject_unref(o);
o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
if (o) {
pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
} else {
pm->s4_val = false;
}
- qobject_decref(o);
+ qobject_unref(o);
pm->pcihp_bridge_en =
object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
}
}
aml_append(parent_scope, method);
- qobject_decref(bsel);
+ qobject_unref(bsel);
}
/**
(void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
}
-#define HOLE_640K_START (640 * 1024)
-#define HOLE_640K_END (1024 * 1024)
+#define HOLE_640K_START (640 * KiB)
+#define HOLE_640K_END (1 * MiB)
static void build_srat_hotpluggable_memory(GArray *table_data, uint64_t base,
uint64_t len, int default_node)
{
- MemoryDeviceInfoList *info_list = qmp_pc_dimm_device_list();
+ MemoryDeviceInfoList *info_list = qmp_memory_device_list();
MemoryDeviceInfoList *info;
MemoryDeviceInfo *mi;
PCDIMMDeviceInfo *di;
const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
PCMachineState *pcms = PC_MACHINE(machine);
ram_addr_t hotplugabble_address_space_size =
- object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
+ object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
NULL);
srat_start = table_data->len;
* providing _PXM method if necessary.
*/
if (hotplugabble_address_space_size) {
- build_srat_hotpluggable_memory(table_data, pcms->hotplug_memory.base,
+ build_srat_hotpluggable_memory(table_data, machine->device_memory->base,
hotplugabble_address_space_size,
pcms->numa_nodes - 1);
}
(1UL << 7), /* PPRSup */
1);
/* IVHD length */
- build_append_int_noprefix(table_data, 0x24, 2);
+ build_append_int_noprefix(table_data, 28, 2);
/* DeviceID */
build_append_int_noprefix(table_data, s->devid, 2);
/* Capability offset */
return false;
}
mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
- qobject_decref(o);
+ qobject_unref(o);
o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
assert(o);
mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
- qobject_decref(o);
+ qobject_unref(o);
return true;
}