#include "acpi-common.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
-#include "hw/pci/pci.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/cxl/cxl.h"
#include "hw/core/cpu.h"
#include "target/i386/cpu.h"
-#include "hw/misc/pvpanic.h"
#include "hw/timer/hpet.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
-#include "hw/isa/isa.h"
+#include "hw/acpi/acpi_aml_interface.h"
#include "hw/input/i8042.h"
-#include "hw/block/fdc.h"
#include "hw/acpi/memory_hotplug.h"
#include "sysemu/tpm.h"
#include "hw/acpi/tpm.h"
#include "hw/acpi/vmgenid.h"
#include "hw/acpi/erst.h"
+#include "hw/acpi/piix4.h"
#include "sysemu/tpm_backend.h"
#include "hw/rtc/mc146818rtc_regs.h"
#include "migration/vmstate.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/ich9.h"
#include "hw/pci/pci_bus.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/pci-host/q35.h"
#include "hw/i386/x86-iommu.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
#include "hw/acpi/pci.h"
+#include "hw/acpi/cxl.h"
#include "qom/qom-qobject.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
#include "hw/virtio/virtio-iommu.h"
-#include "hw/acpi/ipmi.h"
#include "hw/acpi/hmat.h"
#include "hw/acpi/viot.h"
} AcpiPmInfo;
typedef struct AcpiMiscInfo {
- bool is_piix4;
bool has_hpet;
#ifdef CONFIG_TPM
TPMVersion tpm_version;
#endif
- const unsigned char *dsdt_code;
- unsigned dsdt_size;
- uint16_t pvpanic_port;
- uint16_t applesmc_io_base;
} AcpiMiscInfo;
-typedef struct AcpiBuildPciBusHotplugState {
- GArray *device_table;
- GArray *notify_table;
- struct AcpiBuildPciBusHotplugState *parent;
- bool pcihp_bridge_en;
-} AcpiBuildPciBusHotplugState;
-
typedef struct FwCfgTPMConfig {
uint32_t tpmppi_address;
uint8_t tpm_version;
static void acpi_get_misc_info(AcpiMiscInfo *info)
{
- Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
- Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
- assert(!!piix != !!lpc);
-
- if (piix) {
- info->is_piix4 = true;
- }
- if (lpc) {
- info->is_piix4 = false;
- }
-
info->has_hpet = hpet_find();
#ifdef CONFIG_TPM
info->tpm_version = tpm_get_version(tpm_find());
#endif
- info->pvpanic_port = pvpanic_port();
- info->applesmc_io_base = applesmc_port();
}
/*
g_array_append_vals(table_data, reserved, 40); /* Reserved */
}
+Aml *aml_pci_device_dsm(void)
+{
+ Aml *method;
+
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ {
+ Aml *params = aml_local(0);
+ Aml *pkg = aml_package(2);
+ aml_append(pkg, aml_name("BSEL"));
+ aml_append(pkg, aml_name("ASUN"));
+ aml_append(method, aml_store(pkg, params));
+ aml_append(method,
+ aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3), params))
+ );
+ }
+ return method;
+}
+
static void build_append_pcihp_notify_entry(Aml *method, int slot)
{
Aml *if_ctx;
aml_append(method, if_ctx);
}
-static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
- bool pcihp_bridge_en)
+static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
{
- Aml *dev, *notify_method = NULL, *method;
- QObject *bsel;
- PCIBus *sec;
- int devfn;
+ const PCIDevice *pdev = bus->devices[devfn];
- bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
- if (bsel) {
- uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+ if (PCI_FUNC(devfn)) {
+ if (IS_PCI_BRIDGE(pdev)) {
+ /*
+ * Ignore only hotplugged PCI bridges on !0 functions, but
+ * allow describing cold plugged bridges on all functions
+ */
+ if (DEVICE(pdev)->hotplugged) {
+ return true;
+ }
+ } else if (!get_dev_aml_func(DEVICE(pdev))) {
+ /*
+ * Ignore all other devices on !0 functions unless they
+ * have AML description (i.e have get_dev_aml_func() != 0)
+ */
+ return true;
+ }
+ }
+ return false;
+}
- aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
- notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
+static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
+{
+ PCIDevice *pdev = bus->devices[devfn];
+ if (pdev) {
+ return is_devfn_ignored_generic(devfn, bus) ||
+ !DEVICE_GET_CLASS(pdev)->hotpluggable ||
+ /* Cold plugged bridges aren't themselves hot-pluggable */
+ (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
+ } else { /* non populated slots */
+ /*
+ * hotplug is supported only for non-multifunction device
+ * so generate device description only for function 0
+ */
+ if (PCI_FUNC(devfn) ||
+ (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
+ return true;
+ }
}
+ return false;
+}
+
+static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus,
+ QObject *bsel)
+{
+ int devfn;
+ Aml *dev, *notify_method = NULL, *method;
+ uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+
+ aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
+ notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
- DeviceClass *dc;
- PCIDeviceClass *pc;
- PCIDevice *pdev = bus->devices[devfn];
int slot = PCI_SLOT(devfn);
- int func = PCI_FUNC(devfn);
- /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
- int adr = slot << 16 | func;
- bool hotplug_enabled_dev;
- bool bridge_in_acpi;
- bool cold_plugged_bridge;
+ int adr = slot << 16 | PCI_FUNC(devfn);
- if (!pdev) {
- /*
- * add hotplug slots for non present devices.
- * hotplug is supported only for non-multifunction device
- * so generate device description only for function 0
- */
- if (bsel && !func) {
- if (pci_bus_is_express(bus) && slot > 0) {
- break;
- }
- dev = aml_device("S%.02X", devfn);
- aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
- aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
- method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
- aml_append(method,
- aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
- );
- aml_append(dev, method);
- method = aml_method("_DSM", 4, AML_SERIALIZED);
- aml_append(method,
- aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
- aml_arg(2), aml_arg(3),
- aml_name("BSEL"), aml_name("_SUN")))
- );
- aml_append(dev, method);
- aml_append(parent_scope, dev);
-
- build_append_pcihp_notify_entry(notify_method, slot);
- }
+ if (is_devfn_ignored_hotplug(devfn, bus)) {
continue;
}
- pc = PCI_DEVICE_GET_CLASS(pdev);
- dc = DEVICE_GET_CLASS(pdev);
+ if (bus->devices[devfn]) {
+ dev = aml_scope("S%.02X", devfn);
+ } else {
+ dev = aml_device("S%.02X", devfn);
+ aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
+ }
/*
- * Cold plugged bridges aren't themselves hot-pluggable.
- * Hotplugged bridges *are* hot-pluggable.
+ * Can't declare _SUN here for every device as it changes 'slot'
+ * enumeration order in linux kernel, so use another variable for it
*/
- cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
- bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
+ aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
+ aml_append(dev, aml_pci_device_dsm());
- hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
+ aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
+ /* add _EJ0 to make slot hotpluggable */
+ method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
+ aml_append(method,
+ aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
+ );
+ aml_append(dev, method);
- if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
- continue;
- }
+ build_append_pcihp_notify_entry(notify_method, slot);
- /*
- * allow describing coldplugged bridges in ACPI even if they are not
- * on function 0, as they are not unpluggable, for all other devices
- * generate description only for function 0 per slot
- */
- if (func && !bridge_in_acpi) {
+ /* device descriptor has been composed, add it into parent context */
+ aml_append(parent_scope, dev);
+ }
+ aml_append(parent_scope, notify_method);
+}
+
+void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
+{
+ QObject *bsel;
+ int devfn;
+ Aml *dev;
+
+ bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
+
+ for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
+ /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
+ int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
+ PCIDevice *pdev = bus->devices[devfn];
+
+ if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
continue;
}
dev = aml_device("S%.02X", devfn);
aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
- if (bsel) {
- /*
- * Can't declare _SUN here for every device as it changes 'slot'
- * enumeration order in linux kernel, so use another variable for it
- */
- aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
- method = aml_method("_DSM", 4, AML_SERIALIZED);
- aml_append(method, aml_return(
- aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
- aml_arg(3), aml_name("BSEL"), aml_name("ASUN"))
- ));
- aml_append(dev, method);
- }
-
- if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
- /* add VGA specific AML methods */
- int s3d;
-
- if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
- s3d = 3;
- } else {
- s3d = 0;
- }
-
- method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(0)));
- aml_append(dev, method);
-
- method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(0)));
- aml_append(dev, method);
-
- method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(s3d)));
- aml_append(dev, method);
- } else if (hotplug_enabled_dev) {
- aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
- /* add _EJ0 to make slot hotpluggable */
- method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
- aml_append(method,
- aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
- );
- aml_append(dev, method);
+ call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
- if (bsel) {
- build_append_pcihp_notify_entry(notify_method, slot);
- }
- } else if (bridge_in_acpi) {
- /*
- * device is coldplugged bridge,
- * add child device descriptions into its scope
- */
- PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
-
- build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
- }
/* device descriptor has been composed, add it into parent context */
aml_append(parent_scope, dev);
}
if (bsel) {
- aml_append(parent_scope, notify_method);
+ build_append_pcihp_slots(parent_scope, bus, bsel);
}
- /* Append PCNT method to notify about events on local and child buses.
- * Add this method for root bus only when hotplug is enabled since DSDT
- * expects it.
- */
- if (bsel || pcihp_bridge_en) {
- method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
-
- /* If bus supports hotplug select it and notify about local events */
- if (bsel) {
- uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
-
- aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
- aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
- aml_int(1))); /* Device Check */
- aml_append(method, aml_call2("DVNT", aml_name("PCID"),
- aml_int(3))); /* Eject Request */
+ qobject_unref(bsel);
+}
+
+static bool build_append_notfication_callback(Aml *parent_scope,
+ const PCIBus *bus)
+{
+ Aml *method;
+ PCIBus *sec;
+ QObject *bsel;
+ int nr_notifiers = 0;
+
+ QLIST_FOREACH(sec, &bus->child, sibling) {
+ Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
+ if (pci_bus_is_root(sec) ||
+ !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) {
+ continue;
}
+ nr_notifiers = nr_notifiers +
+ build_append_notfication_callback(br_scope, sec);
+ aml_append(parent_scope, br_scope);
+ }
- /* Notify about child bus events in any case */
- if (pcihp_bridge_en) {
- QLIST_FOREACH(sec, &bus->child, sibling) {
- if (pci_bus_is_root(sec)) {
- continue;
- }
+ /*
+ * Append PCNT method to notify about events on local and child buses.
+ * ps: hostbridge might not have hotplug (bsel) enabled but might have
+ * child bridges that do have bsel.
+ */
+ method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_name("^S%.02X.PCNT",
- sec->parent_dev->devfn));
- }
+ /* If bus supports hotplug select it and notify about local events */
+ bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
+ if (bsel) {
+ uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+
+ aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
+ aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
+ aml_int(1))); /* Device Check */
+ aml_append(method, aml_call2("DVNT", aml_name("PCID"),
+ aml_int(3))); /* Eject Request */
+ nr_notifiers++;
+ }
+
+ /* Notify about child bus events in any case */
+ QLIST_FOREACH(sec, &bus->child, sibling) {
+ if (pci_bus_is_root(sec) ||
+ !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) {
+ continue;
}
- aml_append(parent_scope, method);
+ aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
}
+
+ aml_append(parent_scope, method);
qobject_unref(bsel);
+ return !!nr_notifiers;
}
-Aml *aml_pci_device_dsm(void)
+static Aml *aml_pci_pdsm(void)
{
- Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx;
- Aml *acpi_index = aml_local(0);
+ Aml *method, *UUID, *ifctx, *ifctx1;
+ Aml *ret = aml_local(0);
+ Aml *caps = aml_local(1);
+ Aml *acpi_index = aml_local(2);
Aml *zero = aml_int(0);
- Aml *bnum = aml_arg(4);
+ Aml *one = aml_int(1);
Aml *func = aml_arg(2);
Aml *rev = aml_arg(1);
- Aml *sun = aml_arg(5);
+ Aml *params = aml_arg(4);
+ Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
+ Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
+
+ method = aml_method("PDSM", 5, AML_SERIALIZED);
+
+ /* get supported functions */
+ ifctx = aml_if(aml_equal(func, zero));
+ {
+ uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
+ aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret));
+ aml_append(ifctx, aml_store(zero, caps));
+
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6. _DSM Definitions for PCI
+ */
+ UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
+ ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
+ {
+ /* call is for unsupported UUID, bail out */
+ aml_append(ifctx1, aml_return(ret));
+ }
+ aml_append(ifctx, ifctx1);
- method = aml_method("PDSM", 6, AML_SERIALIZED);
+ ifctx1 = aml_if(aml_lless(rev, aml_int(2)));
+ {
+ /* call is for unsupported REV, bail out */
+ aml_append(ifctx1, aml_return(ret));
+ }
+ aml_append(ifctx, ifctx1);
+ aml_append(ifctx,
+ aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
+ /*
+ * advertise function 7 if device has acpi-index
+ * acpi_index values:
+ * 0: not present (default value)
+ * FFFFFFFF: not supported (old QEMU without PIDX reg)
+ * other: device's acpi-index
+ */
+ ifctx1 = aml_if(aml_lnot(
+ aml_or(aml_equal(acpi_index, zero),
+ aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
+ ));
+ {
+ /* have supported functions */
+ aml_append(ifctx1, aml_or(caps, one, caps));
+ /* support for function 7 */
+ aml_append(ifctx1,
+ aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
+ }
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
+ aml_append(ifctx, aml_return(ret));
+ }
+ aml_append(method, ifctx);
+
+ /* handle specific functions requests */
/*
* PCI Firmware Specification 3.1
- * 4.6. _DSM Definitions for PCI
+ * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
+ * Operating Systems
*/
- UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
- ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ ifctx = aml_if(aml_equal(func, aml_int(7)));
{
- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
- ifctx1 = aml_if(aml_equal(func, zero));
- {
- uint8_t byte_list[1];
+ Aml *pkg = aml_package(2);
- ifctx2 = aml_if(aml_equal(rev, aml_int(2)));
- {
- /*
- * advertise function 7 if device has acpi-index
- * acpi_index values:
- * 0: not present (default value)
- * FFFFFFFF: not supported (old QEMU without PIDX reg)
- * other: device's acpi-index
- */
- ifctx3 = aml_if(aml_lnot(
- aml_or(aml_equal(acpi_index, zero),
- aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
- ));
- {
- byte_list[0] =
- 1 /* have supported functions */ |
- 1 << 7 /* support for function 7 */
- ;
- aml_append(ifctx3, aml_return(aml_buffer(1, byte_list)));
- }
- aml_append(ifctx2, ifctx3);
- }
- aml_append(ifctx1, ifctx2);
-
- byte_list[0] = 0; /* nothing supported */
- aml_append(ifctx1, aml_return(aml_buffer(1, byte_list)));
- }
- aml_append(ifctx, ifctx1);
- elsectx = aml_else();
- /*
- * PCI Firmware Specification 3.1
- * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
- * Operating Systems
- */
- ifctx1 = aml_if(aml_equal(func, aml_int(7)));
- {
- Aml *pkg = aml_package(2);
- Aml *ret = aml_local(1);
-
- aml_append(pkg, zero);
- /*
- * optional, if not impl. should return null string
- */
- aml_append(pkg, aml_string("%s", ""));
- aml_append(ifctx1, aml_store(pkg, ret));
- /*
- * update acpi-index to actual value
- */
- aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
- aml_append(ifctx1, aml_return(ret));
- }
- aml_append(elsectx, ifctx1);
- aml_append(ifctx, elsectx);
+ aml_append(pkg, zero);
+ /*
+ * optional, if not impl. should return null string
+ */
+ aml_append(pkg, aml_string("%s", ""));
+ aml_append(ifctx, aml_store(pkg, ret));
+
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
+ /*
+ * update acpi-index to actual value
+ */
+ aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
+ aml_append(ifctx, aml_return(ret));
}
+
aml_append(method, ifctx);
return method;
}
return dev;
}
-static void build_isa_devices_aml(Aml *table)
-{
- bool ambiguous;
- Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
- Aml *scope;
-
- assert(obj && !ambiguous);
-
- scope = aml_scope("_SB.PCI0.ISA");
- build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
- isa_build_aml(ISA_BUS(obj), scope);
-
- aml_append(table, scope);
-}
-
static void build_dbg_aml(Aml *table)
{
Aml *field;
{
Aml *dev;
Aml *crs;
- Aml *field;
Aml *method;
uint32_t irqs;
Aml *sb_scope = aml_scope("_SB");
aml_append(pci0_scope, build_prt(true));
aml_append(sb_scope, pci0_scope);
- field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
- aml_append(field, aml_named_field("PRQ0", 8));
- aml_append(field, aml_named_field("PRQ1", 8));
- aml_append(field, aml_named_field("PRQ2", 8));
- aml_append(field, aml_named_field("PRQ3", 8));
- aml_append(sb_scope, field);
-
aml_append(sb_scope, build_irq_status_method());
aml_append(sb_scope, build_iqcr_method(true));
static void build_q35_pci0_int(Aml *table)
{
- Aml *field;
Aml *method;
Aml *sb_scope = aml_scope("_SB");
Aml *pci0_scope = aml_scope("PCI0");
aml_append(pci0_scope, method);
aml_append(sb_scope, pci0_scope);
- field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
- aml_append(field, aml_named_field("PRQA", 8));
- aml_append(field, aml_named_field("PRQB", 8));
- aml_append(field, aml_named_field("PRQC", 8));
- aml_append(field, aml_named_field("PRQD", 8));
- aml_append(field, aml_reserved_field(0x20));
- aml_append(field, aml_named_field("PRQE", 8));
- aml_append(field, aml_named_field("PRQF", 8));
- aml_append(field, aml_named_field("PRQG", 8));
- aml_append(field, aml_named_field("PRQH", 8));
- aml_append(sb_scope, field);
-
aml_append(sb_scope, build_irq_status_method());
aml_append(sb_scope, build_iqcr_method(false));
return dev;
}
-static void build_q35_isa_bridge(Aml *table)
-{
- Aml *dev;
- Aml *scope;
-
- scope = aml_scope("_SB.PCI0");
- dev = aml_device("ISA");
- aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
-
- /* ICH9 PCI to ISA irq remapping */
- aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
- aml_int(0x60), 0x0C));
-
- aml_append(scope, dev);
- aml_append(table, scope);
-}
-
-static void build_piix4_isa_bridge(Aml *table)
-{
- Aml *dev;
- Aml *scope;
-
- scope = aml_scope("_SB.PCI0");
- dev = aml_device("ISA");
- aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
-
- /* PIIX PCI to ISA irq remapping */
- aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
- aml_int(0x60), 0x04));
-
- aml_append(scope, dev);
- aml_append(table, scope);
-}
-
static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
{
Aml *scope;
aml_append(method, aml_return(aml_local(0)));
aml_append(scope, method);
- aml_append(scope, aml_pci_device_dsm());
+ aml_append(scope, aml_pci_pdsm());
aml_append(table, scope);
}
return method;
}
-static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
+static void build_acpi0017(Aml *table)
{
- Aml *scope = aml_scope("_SB.PCI0");
- Aml *dev = aml_device("SMB0");
+ Aml *dev, *scope, *method;
+
+ scope = aml_scope("_SB");
+ dev = aml_device("CXLM");
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x01)));
+ aml_append(dev, method);
- aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
- build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
aml_append(scope, dev);
aml_append(table, scope);
}
AcpiPmInfo *pm, AcpiMiscInfo *misc,
Range *pci_hole, Range *pci_hole64, MachineState *machine)
{
+ Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE);
+ Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE);
CrsRangeEntry *entry;
Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
CrsRangeSet crs_range_set;
#ifdef CONFIG_TPM
TPMIf *tpm = tpm_find();
#endif
+ bool cxl_present = false;
int i;
VMBusBridge *vmbus_bridge = vmbus_bridge_find();
AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
.oem_table_id = x86ms->oem_table_id };
+ assert(!!i440fx != !!q35);
+
acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
build_dbg_aml(dsdt);
- if (misc->is_piix4) {
+ if (i440fx) {
sb_scope = aml_scope("_SB");
dev = aml_device("PCI0");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
aml_append(sb_scope, dev);
aml_append(dsdt, sb_scope);
- if (misc->has_hpet) {
- build_hpet_aml(dsdt);
- }
- build_piix4_isa_bridge(dsdt);
- build_isa_devices_aml(dsdt);
if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
build_piix4_pci0_int(dsdt);
- } else {
+ } else if (q35) {
sb_scope = aml_scope("_SB");
dev = aml_device("PCI0");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
aml_append(dsdt, sb_scope);
- if (misc->has_hpet) {
- build_hpet_aml(dsdt);
- }
- build_q35_isa_bridge(dsdt);
- build_isa_devices_aml(dsdt);
if (pm->pcihp_bridge_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
build_q35_pci0_int(dsdt);
- if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
- build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
- }
+ }
+
+ if (misc->has_hpet) {
+ build_hpet_aml(dsdt);
}
if (vmbus_bridge) {
aml_append(dsdt, sb_scope);
}
+ scope = aml_scope("_GPE");
+ {
+ aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
+ if (machine->nvdimms_state->is_enabled) {
+ method = aml_method("_E04", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
+ aml_int(0x80)));
+ aml_append(scope, method);
+ }
+ }
+ aml_append(dsdt, scope);
+
if (pcmc->legacy_cpu_hotplug) {
build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
} else {
pcms->memhp_io_base);
}
- scope = aml_scope("_GPE");
- {
- aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
-
- if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
- method = aml_method("_E01", 0, AML_NOTSERIALIZED);
- aml_append(method,
- aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
- aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
- aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
- aml_append(scope, method);
- }
-
- if (machine->nvdimms_state->is_enabled) {
- method = aml_method("_E04", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
- aml_int(0x80)));
- aml_append(scope, method);
- }
- }
- aml_append(dsdt, scope);
-
crs_range_set_init(&crs_range_set);
bus = PC_MACHINE(machine)->bus;
if (bus) {
}
scope = aml_scope("\\_SB");
- dev = aml_device("PC%.02X", bus_num);
+
+ if (pci_bus_is_cxl(bus)) {
+ dev = aml_device("CL%.02X", bus_num);
+ } else {
+ dev = aml_device("PC%.02X", bus_num);
+ }
aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
- if (pci_bus_is_express(bus)) {
+ if (pci_bus_is_cxl(bus)) {
+ struct Aml *pkg = aml_package(2);
+
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
+ aml_append(pkg, aml_eisaid("PNP0A08"));
+ aml_append(pkg, aml_eisaid("PNP0A03"));
+ aml_append(dev, aml_name_decl("_CID", pkg));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
+ build_cxl_osc_method(dev);
+ } else if (pci_bus_is_express(bus)) {
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(dsdt, scope);
+
+ /* Handle the ranges for the PXB expanders */
+ if (pci_bus_is_cxl(bus)) {
+ MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
+ uint64_t base = mr->addr;
+
+ cxl_present = true;
+ crs_range_insert(crs_range_set.mem_ranges, base,
+ base + memory_region_size(mr) - 1);
+ }
}
}
+ if (cxl_present) {
+ build_acpi0017(dsdt);
+ }
+
/*
* At this point crs_range_set has all the ranges used by pci
* busses *other* than PCI0. These ranges will be excluded from
aml_append(dsdt, scope);
}
- if (misc->applesmc_io_base) {
- scope = aml_scope("\\_SB.PCI0.ISA");
- dev = aml_device("SMC");
-
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
- /* device present, functioning, decoding, not shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-
- crs = aml_resource_template();
- aml_append(crs,
- aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
- 0x01, APPLESMC_MAX_DATA_LENGTH)
- );
- aml_append(crs, aml_irq_no_flags(6));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- aml_append(scope, dev);
- aml_append(dsdt, scope);
- }
-
- if (misc->pvpanic_port) {
- scope = aml_scope("\\_SB.PCI0.ISA");
-
- dev = aml_device("PEVT");
- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
-
- crs = aml_resource_template();
- aml_append(crs,
- aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
- );
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
- aml_int(misc->pvpanic_port), 1));
- field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
- aml_append(field, aml_named_field("PEPT", 8));
- aml_append(dev, field);
-
- /* device present, functioning, decoding, shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
-
- method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
- aml_append(method, aml_return(aml_local(0)));
- aml_append(dev, method);
-
- method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
- aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
- aml_append(dev, method);
-
- aml_append(scope, dev);
- aml_append(dsdt, scope);
- }
-
sb_scope = aml_scope("\\_SB");
{
- Object *pci_host;
- PCIBus *bus = NULL;
-
- pci_host = acpi_get_i386_pci_host();
+ Object *pci_host = acpi_get_i386_pci_host();
if (pci_host) {
- bus = PCI_HOST_BRIDGE(pci_host)->bus;
- }
-
- if (bus) {
+ PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
Aml *scope = aml_scope("PCI0");
/* Scan all PCI buses. Generate tables to support hotplug. */
- build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
-
-#ifdef CONFIG_TPM
- if (TPM_IS_TIS_ISA(tpm)) {
- if (misc->tpm_version == TPM_VERSION_2_0) {
- dev = aml_device("TPM");
- aml_append(dev, aml_name_decl("_HID",
- aml_string("MSFT0101")));
- aml_append(dev,
- aml_name_decl("_STR",
- aml_string("TPM 2.0 Device")));
- } else {
- dev = aml_device("ISA.TPM");
- aml_append(dev, aml_name_decl("_HID",
- aml_eisaid("PNP0C31")));
- }
- aml_append(dev, aml_name_decl("_UID", aml_int(1)));
-
- aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
- crs = aml_resource_template();
- aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
- TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
- /*
- FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
- Rewrite to take IRQ from TPM device model and
- fix default IRQ value there to use some unused IRQ
- */
- /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- tpm_build_ppi_acpi(tpm, dev);
-
- aml_append(scope, dev);
- }
-#endif
-
+ build_append_pci_bus_devices(scope, bus);
aml_append(sb_scope, scope);
}
}
}
aml_append(dsdt, sb_scope);
+ if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
+ bool has_pcnt;
+
+ Object *pci_host = acpi_get_i386_pci_host();
+ PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
+
+ scope = aml_scope("\\_SB.PCI0");
+ has_pcnt = build_append_notfication_callback(scope, bus);
+ if (has_pcnt) {
+ aml_append(dsdt, scope);
+ }
+
+ scope = aml_scope("_GPE");
+ {
+ method = aml_method("_E01", 0, AML_NOTSERIALIZED);
+ if (has_pcnt) {
+ aml_append(method,
+ aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
+ aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
+ aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
+ }
+ aml_append(scope, method);
+ }
+ aml_append(dsdt, scope);
+ }
+
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
acpi_table_end(linker, &table);
build_srat_memory(table_data, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
- mem_base = 1ULL << 32;
+ mem_base = x86ms->above_4g_mem_start;
mem_len = next_base - x86ms->below_4g_mem_size;
next_base = mem_base + mem_len;
}
machine->nvdimms_state, machine->ram_slots,
x86ms->oem_id, x86ms->oem_table_id);
}
+ if (pcms->cxl_devices_state.is_enabled) {
+ cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+ x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
+ }
acpi_add_table(table_offsets, tables_blob);
build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
projects / mirror_qemu.git / blobdiff