* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include <hw/hw.h>
-#include <hw/i386/pc.h>
-#include <hw/pci/pci.h>
-#include <hw/isa/isa.h>
-#include "block/block.h"
-#include "sysemu/sysemu.h"
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/module.h"
+#include "hw/isa/isa.h"
#include "sysemu/dma.h"
+#include "sysemu/reset.h"
-#include <hw/ide/pci.h>
+#include "hw/ide/pci.h"
+#include "trace.h"
/* CMD646 specific */
#define CFR 0x50
static void cmd646_update_irq(PCIDevice *pd);
-static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
- unsigned size)
-{
- CMD646BAR *cmd646bar = opaque;
-
- if (addr != 2 || size != 1) {
- return ((uint64_t)1 << (size * 8)) - 1;
- }
- return ide_status_read(cmd646bar->bus, addr + 2);
-}
-
-static void cmd646_cmd_write(void *opaque, hwaddr addr,
- uint64_t data, unsigned size)
-{
- CMD646BAR *cmd646bar = opaque;
-
- if (addr != 2 || size != 1) {
- return;
- }
- ide_cmd_write(cmd646bar->bus, addr + 2, data);
-}
-
-static const MemoryRegionOps cmd646_cmd_ops = {
- .read = cmd646_cmd_read,
- .write = cmd646_cmd_write,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
- unsigned size)
-{
- CMD646BAR *cmd646bar = opaque;
-
- if (size == 1) {
- return ide_ioport_read(cmd646bar->bus, addr);
- } else if (addr == 0) {
- if (size == 2) {
- return ide_data_readw(cmd646bar->bus, addr);
- } else {
- return ide_data_readl(cmd646bar->bus, addr);
- }
- }
- return ((uint64_t)1 << (size * 8)) - 1;
-}
-
-static void cmd646_data_write(void *opaque, hwaddr addr,
- uint64_t data, unsigned size)
-{
- CMD646BAR *cmd646bar = opaque;
-
- if (size == 1) {
- ide_ioport_write(cmd646bar->bus, addr, data);
- } else if (addr == 0) {
- if (size == 2) {
- ide_data_writew(cmd646bar->bus, addr, data);
- } else {
- ide_data_writel(cmd646bar->bus, addr, data);
- }
- }
-}
-
-static const MemoryRegionOps cmd646_data_ops = {
- .read = cmd646_data_read,
- .write = cmd646_data_write,
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
-{
- IDEBus *bus = &d->bus[bus_num];
- CMD646BAR *bar = &d->cmd646_bar[bus_num];
-
- bar->bus = bus;
- bar->pci_dev = d;
- memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
- "cmd646-cmd", 4);
- memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
- "cmd646-data", 8);
-}
-
static void cmd646_update_dma_interrupts(PCIDevice *pd)
{
/* Sync DMA interrupt status from UDMA interrupt status */
val = 0xff;
break;
}
-#ifdef DEBUG_IDE
- printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
-#endif
+
+ trace_bmdma_read_cmd646(addr, val);
return val;
}
return;
}
-#ifdef DEBUG_IDE
- printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
-#endif
+ trace_bmdma_write_cmd646(addr, val);
switch(addr & 3) {
case 0:
bmdma_cmd_writeb(bm, val);
}
/* CMD646 PCI IDE controller */
-static int pci_cmd646_ide_initfn(PCIDevice *dev)
+static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
dev->wmask[MRDMODE] = 0x0;
dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
- setup_cmd646_bar(d, 0);
- setup_cmd646_bar(d, 1);
- pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
- pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
- pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
- pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
+ memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
+ &d->bus[0], "cmd646-data0", 8);
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
+
+ memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
+ &d->bus[0], "cmd646-cmd0", 4);
+ pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
+
+ memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
+ &d->bus[1], "cmd646-data1", 8);
+ pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
+
+ memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
+ &d->bus[1], "cmd646-cmd1", 4);
+ pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
+
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
- qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
- &d->bmdma[i].dma);
+ ide_register_restart_cb(&d->bus[i]);
}
+ g_free(irq);
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
- return 0;
}
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
for (i = 0; i < 2; ++i) {
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
- memory_region_destroy(&d->bmdma[i].extra_io);
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
- memory_region_destroy(&d->bmdma[i].addr_ioport);
- memory_region_destroy(&d->cmd646_bar[i].cmd);
- memory_region_destroy(&d->cmd646_bar[i].data);
}
- memory_region_destroy(&d->bmdma_bar);
}
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->init = pci_cmd646_ide_initfn;
+ k->realize = pci_cmd646_ide_realize;
k->exit = pci_cmd646_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_CMD;
k->device_id = PCI_DEVICE_ID_CMD_646;
k->config_read = cmd646_pci_config_read;
k->config_write = cmd646_pci_config_write;
dc->props = cmd646_ide_properties;
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static const TypeInfo cmd646_ide_info = {
projects / mirror_qemu.git / blobdiff