* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/ppc/mac_dbdma.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/module.h"
+#include "hw/misc/macio/macio.h"
#include "sysemu/block-backend.h"
#include "sysemu/dma.h"
break;
case IDE_DMA_TRIM:
s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
- offset, 0x1, ide_issue_trim, s->blk,
+ offset, 0x1, ide_issue_trim, s,
pmac_ide_transfer_cb, io,
DMA_DIRECTION_TO_DEVICE);
break;
}
/* PowerMac IDE memory IO */
-static void pmac_ide_writeb (void *opaque,
- hwaddr addr, uint32_t val)
+static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
{
MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- switch (addr) {
- case 1 ... 7:
- ide_ioport_write(&d->bus, addr, val);
- break;
- case 8:
- case 22:
- ide_cmd_write(&d->bus, 0, val);
+ uint64_t retval = 0xffffffff;
+ int reg = addr >> 4;
+
+ switch (reg) {
+ case 0x0:
+ if (size == 2) {
+ retval = ide_data_readw(&d->bus, 0);
+ } else if (size == 4) {
+ retval = ide_data_readl(&d->bus, 0);
+ }
break;
- default:
+ case 0x1 ... 0x7:
+ if (size == 1) {
+ retval = ide_ioport_read(&d->bus, reg);
+ }
break;
- }
-}
-
-static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
-{
- uint8_t retval;
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- switch (addr) {
- case 1 ... 7:
- retval = ide_ioport_read(&d->bus, addr);
+ case 0x8:
+ case 0x16:
+ if (size == 1) {
+ retval = ide_status_read(&d->bus, 0);
+ }
break;
- case 8:
- case 22:
- retval = ide_status_read(&d->bus, 0);
+ case 0x20:
+ if (size == 4) {
+ retval = d->timing_reg;
+ }
break;
- default:
- retval = 0xFF;
+ case 0x30:
+ /* This is an interrupt state register that only exists
+ * in the KeyLargo and later variants. Bit 0x8000_0000
+ * latches the DMA interrupt and has to be written to
+ * clear. Bit 0x4000_0000 is an image of the disk
+ * interrupt. MacOS X relies on this and will hang if
+ * we don't provide at least the disk interrupt
+ */
+ if (size == 4) {
+ retval = d->irq_reg;
+ }
break;
}
- return retval;
-}
-
-static void pmac_ide_writew (void *opaque,
- hwaddr addr, uint32_t val)
-{
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- val = bswap16(val);
- if (addr == 0) {
- ide_data_writew(&d->bus, 0, val);
- }
-}
-static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
-{
- uint16_t retval;
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- if (addr == 0) {
- retval = ide_data_readw(&d->bus, 0);
- } else {
- retval = 0xFFFF;
- }
- retval = bswap16(retval);
return retval;
}
-static void pmac_ide_writel (void *opaque,
- hwaddr addr, uint32_t val)
-{
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- val = bswap32(val);
- if (addr == 0) {
- ide_data_writel(&d->bus, 0, val);
- }
-}
-static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
+static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
{
- uint32_t retval;
MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- if (addr == 0) {
- retval = ide_data_readl(&d->bus, 0);
- } else {
- retval = 0xFFFFFFFF;
+ int reg = addr >> 4;
+
+ switch (reg) {
+ case 0x0:
+ if (size == 2) {
+ ide_data_writew(&d->bus, 0, val);
+ } else if (size == 4) {
+ ide_data_writel(&d->bus, 0, val);
+ }
+ break;
+ case 0x1 ... 0x7:
+ if (size == 1) {
+ ide_ioport_write(&d->bus, reg, val);
+ }
+ break;
+ case 0x8:
+ case 0x16:
+ if (size == 1) {
+ ide_cmd_write(&d->bus, 0, val);
+ }
+ break;
+ case 0x20:
+ if (size == 4) {
+ d->timing_reg = val;
+ }
+ break;
+ case 0x30:
+ if (size == 4) {
+ if (val & 0x80000000u) {
+ d->irq_reg &= 0x7fffffff;
+ }
+ }
+ break;
}
- retval = bswap32(retval);
- return retval;
}
static const MemoryRegionOps pmac_ide_ops = {
- .old_mmio = {
- .write = {
- pmac_ide_writeb,
- pmac_ide_writew,
- pmac_ide_writel,
- },
- .read = {
- pmac_ide_readb,
- pmac_ide_readw,
- pmac_ide_readl,
- },
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .read = pmac_ide_read,
+ .write = pmac_ide_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_pmac = {
.name = "ide",
- .version_id = 4,
+ .version_id = 5,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MACIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
VMSTATE_BOOL(dma_active, MACIOIDEState),
+ VMSTATE_UINT32(timing_reg, MACIOIDEState),
+ VMSTATE_UINT32(irq_reg, MACIOIDEState),
VMSTATE_END_OF_LIST()
}
};
ide_bus_reset(&d->bus);
}
-static int ide_nop_int(IDEDMA *dma, int x)
+static int ide_nop_int(IDEDMA *dma, bool is_write)
{
return 0;
}
{
MACIOIDEState *s = MACIO_IDE(dev);
- ide_init2(&s->bus, s->irq);
+ ide_init2(&s->bus, s->ide_irq);
/* Register DMA callbacks */
s->dma.ops = &dbdma_ops;
s->bus.dma = &s->dma;
}
+static void pmac_ide_irq(void *opaque, int n, int level)
+{
+ MACIOIDEState *s = opaque;
+ uint32_t mask = 0x80000000u >> n;
+
+ /* We need to reflect the IRQ state in the irq register */
+ if (level) {
+ s->irq_reg |= mask;
+ } else {
+ s->irq_reg &= ~mask;
+ }
+
+ if (n) {
+ qemu_set_irq(s->real_ide_irq, level);
+ } else {
+ qemu_set_irq(s->real_dma_irq, level);
+ }
+}
+
static void macio_ide_initfn(Object *obj)
{
SysBusDevice *d = SYS_BUS_DEVICE(obj);
ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
sysbus_init_mmio(d, &s->mem);
- sysbus_init_irq(d, &s->irq);
- sysbus_init_irq(d, &s->dma_irq);
+ sysbus_init_irq(d, &s->real_ide_irq);
+ sysbus_init_irq(d, &s->real_dma_irq);
+ s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);
+ s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);
+
+ object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
+ (Object **) &s->dbdma,
+ qdev_prop_allow_set_link_before_realize, 0);
}
+static Property macio_ide_properties[] = {
+ DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
+ DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void macio_ide_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = macio_ide_realizefn;
dc->reset = macio_ide_reset;
+ device_class_set_props(dc, macio_ide_properties);
dc->vmsd = &vmstate_pmac;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
}
}
-void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
+void macio_ide_register_dma(MACIOIDEState *s)
{
- s->dbdma = dbdma;
- DBDMA_register_channel(dbdma, channel, s->dma_irq,
+ DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq,
pmac_ide_transfer, pmac_ide_flush, s);
}
projects / mirror_qemu.git / blobdiff