* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "hw/i386/pc.h"
#include "hw/input/ps2.h"
+#include "hw/input/i8042.h"
#include "sysemu/sysemu.h"
-/* debug PC keyboard */
-//#define DEBUG_KBD
-#ifdef DEBUG_KBD
-#define DPRINTF(fmt, ...) \
- do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
/* Keyboard Controller Commands */
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
#define KBD_CCMD_WRITE_OBUF 0xD2
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
+ initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+/* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
+ * We make the default value of the outport include these four bits,
+ * so that the subsection is rarely necessary.
+ */
+#define KBD_OUT_ONES 0xcc
+
/* Mouse Commands */
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
uint8_t status;
uint8_t mode;
uint8_t outport;
+ bool outport_present;
/* Bitmask of devices with data available. */
uint8_t pending;
void *kbd;
qemu_irq irq_kbd;
qemu_irq irq_mouse;
- qemu_irq *a20_out;
+ qemu_irq a20_out;
hwaddr mask;
} KBDState;
KBDState *s = opaque;
int val;
val = s->status;
- DPRINTF("kbd: read status=0x%02x\n", val);
+ trace_pckbd_kbd_read_status(val);
return val;
}
static void outport_write(KBDState *s, uint32_t val)
{
- DPRINTF("kbd: write outport=0x%02x\n", val);
+ trace_pckbd_outport_write(val);
s->outport = val;
- if (s->a20_out) {
- qemu_set_irq(*s->a20_out, (val >> 1) & 1);
- }
+ qemu_set_irq(s->a20_out, (val >> 1) & 1);
if (!(val & 1)) {
- qemu_system_reset_request();
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
{
KBDState *s = opaque;
- DPRINTF("kbd: write cmd=0x%02x\n", val);
+ trace_pckbd_kbd_write_command(val);
/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
kbd_update_irq(s);
break;
case KBD_CCMD_READ_INPORT:
- kbd_queue(s, 0x00, 0);
+ kbd_queue(s, 0x80, 0);
break;
case KBD_CCMD_READ_OUTPORT:
kbd_queue(s, s->outport, 0);
break;
case KBD_CCMD_ENABLE_A20:
- if (s->a20_out) {
- qemu_irq_raise(*s->a20_out);
- }
+ qemu_irq_raise(s->a20_out);
s->outport |= KBD_OUT_A20;
break;
case KBD_CCMD_DISABLE_A20:
- if (s->a20_out) {
- qemu_irq_lower(*s->a20_out);
- }
+ qemu_irq_lower(s->a20_out);
s->outport &= ~KBD_OUT_A20;
break;
case KBD_CCMD_RESET:
- qemu_system_reset_request();
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
break;
case KBD_CCMD_NO_OP:
/* ignore that */
break;
default:
- fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
break;
}
}
else
val = ps2_read_data(s->kbd);
- DPRINTF("kbd: read data=0x%02x\n", val);
+ trace_pckbd_kbd_read_data(val);
return val;
}
{
KBDState *s = opaque;
- DPRINTF("kbd: write data=0x%02x\n", val);
+ trace_pckbd_kbd_write_data(val);
switch(s->write_cmd) {
case 0:
s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
- s->outport = KBD_OUT_RESET | KBD_OUT_A20;
+ s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
+ s->outport_present = false;
+}
+
+static uint8_t kbd_outport_default(KBDState *s)
+{
+ return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
+ | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
+ | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
+}
+
+static int kbd_outport_post_load(void *opaque, int version_id)
+{
+ KBDState *s = opaque;
+ s->outport_present = true;
+ return 0;
+}
+
+static bool kbd_outport_needed(void *opaque)
+{
+ KBDState *s = opaque;
+ return s->outport != kbd_outport_default(s);
+}
+
+static const VMStateDescription vmstate_kbd_outport = {
+ .name = "pckbd_outport",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = kbd_outport_post_load,
+ .needed = kbd_outport_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(outport, KBDState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int kbd_post_load(void *opaque, int version_id)
+{
+ KBDState *s = opaque;
+ if (!s->outport_present) {
+ s->outport = kbd_outport_default(s);
+ }
+ s->outport_present = false;
+ return 0;
}
static const VMStateDescription vmstate_kbd = {
.name = "pckbd",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 3,
- .fields = (VMStateField []) {
+ .post_load = kbd_post_load,
+ .fields = (VMStateField[]) {
VMSTATE_UINT8(write_cmd, KBDState),
VMSTATE_UINT8(status, KBDState),
VMSTATE_UINT8(mode, KBDState),
VMSTATE_UINT8(pending, KBDState),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription*[]) {
+ &vmstate_kbd_outport,
+ NULL
}
};
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
+static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
{
KBDState *s = opaque;
return kbd_read_data(s, 0, 1) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
+static void kbd_mm_writefn(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
KBDState *s = opaque;
kbd_write_data(s, 0, value & 0xff, 1);
}
+
static const MemoryRegionOps i8042_mmio_ops = {
+ .read = kbd_mm_readfn,
+ .write = kbd_mm_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
- .old_mmio = {
- .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
- .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
- },
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
qemu_register_reset(kbd_reset, s);
}
-#define TYPE_I8042 "i8042"
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
typedef struct ISAKBDState {
ps2_mouse_fake_event(s->mouse);
}
-void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
+void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
{
- ISAKBDState *isa = I8042(dev);
- KBDState *s = &isa->kbd;
-
- s->a20_out = a20_out;
+ qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
}
static const VMStateDescription vmstate_kbd_isa = {
.name = "pckbd",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 3,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
VMSTATE_END_OF_LIST()
}
"i8042-data", 1);
memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
"i8042-cmd", 1);
+
+ qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
}
static void i8042_realizefn(DeviceState *dev, Error **errp)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = i8042_realizefn;
- dc->no_user = 1;
dc->vmsd = &vmstate_kbd_isa;
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo i8042_info = {
projects / mirror_qemu.git / blobdiff