* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw/hw.h"
-#include "hw/i386/pc.h"
+
+#include "qemu/osdep.h"
+#include "hw/intc/i8259.h"
+#include "hw/irq.h"
#include "hw/isa/isa.h"
-#include "monitor/monitor.h"
#include "qemu/timer.h"
+#include "qemu/log.h"
#include "hw/isa/i8259_internal.h"
+#include "trace.h"
+#include "qom/object.h"
/* debug PIC */
//#define DEBUG_PIC
-#ifdef DEBUG_PIC
-#define DPRINTF(fmt, ...) \
- do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif
-
//#define DEBUG_IRQ_LATENCY
-//#define DEBUG_IRQ_COUNT
#define TYPE_I8259 "isa-i8259"
-#define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259)
-#define PIC_GET_CLASS(obj) OBJECT_GET_CLASS(PICClass, (obj), TYPE_I8259)
+typedef struct PICClass PICClass;
+DECLARE_CLASS_CHECKERS(PICClass, PIC,
+ TYPE_I8259)
/**
* PICClass:
* @parent_realize: The parent's realizefn.
*/
-typedef struct PICClass {
+struct PICClass {
PICCommonClass parent_class;
DeviceRealize parent_realize;
-} PICClass;
+};
-#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
-static int irq_level[16];
-#endif
-#ifdef DEBUG_IRQ_COUNT
-static uint64_t irq_count[16];
-#endif
#ifdef DEBUG_IRQ_LATENCY
static int64_t irq_time[16];
#endif
-DeviceState *isa_pic;
+PICCommonState *isa_pic;
static PICCommonState *slave_pic;
/* return the highest priority found in mask (highest = smallest
irq = pic_get_irq(s);
if (irq >= 0) {
- DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
- s->master ? 0 : 1, s->imr, s->irr, s->priority_add);
+ trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add);
qemu_irq_raise(s->int_out[0]);
} else {
qemu_irq_lower(s->int_out[0]);
{
PICCommonState *s = opaque;
int mask = 1 << irq;
-
-#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
- defined(DEBUG_IRQ_LATENCY)
int irq_index = s->master ? irq : irq + 8;
-#endif
-#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
- if (level != irq_level[irq_index]) {
- DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level);
- irq_level[irq_index] = level;
-#ifdef DEBUG_IRQ_COUNT
- if (level == 1) {
- irq_count[irq_index]++;
- }
-#endif
- }
-#endif
+
+ trace_pic_set_irq(s->master, irq, level);
+ pic_stat_update_irq(irq_index, level);
+
#ifdef DEBUG_IRQ_LATENCY
if (level) {
irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
#endif
- if (s->elcr & mask) {
+ if (s->ltim || (s->elcr & mask)) {
/* level triggered */
if (level) {
s->irr |= mask;
s->isr |= (1 << irq);
}
/* We don't clear a level sensitive interrupt here */
- if (!(s->elcr & (1 << irq))) {
+ if (!s->ltim && !(s->elcr & (1 << irq))) {
s->irr &= ~(1 << irq);
}
pic_update_irq(s);
}
-int pic_read_irq(DeviceState *d)
+int pic_read_irq(PICCommonState *s)
{
- PICCommonState *s = PIC_COMMON(d);
- int irq, irq2, intno;
+ int irq, intno;
irq = pic_get_irq(s);
if (irq >= 0) {
+ int irq2;
+
if (irq == 2) {
irq2 = pic_get_irq(slave_pic);
if (irq2 >= 0) {
irq2 = 7;
}
intno = slave_pic->irq_base + irq2;
+ pic_intack(s, irq);
+ irq = irq2 + 8;
} else {
intno = s->irq_base + irq;
+ pic_intack(s, irq);
}
- pic_intack(s, irq);
} else {
/* spurious IRQ on host controller */
irq = 7;
intno = s->irq_base + irq;
}
-#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
- if (irq == 2) {
- irq = irq2 + 8;
- }
-#endif
#ifdef DEBUG_IRQ_LATENCY
printf("IRQ%d latency=%0.3fus\n",
irq,
(double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
- irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
+ irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND);
#endif
- DPRINTF("pic_interrupt: irq=%d\n", irq);
+
+ trace_pic_interrupt(irq, intno);
return intno;
}
PICCommonState *s = PIC_COMMON(dev);
s->elcr = 0;
+ s->ltim = 0;
pic_init_reset(s);
}
uint32_t val = val64;
int priority, cmd, irq;
- DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
+ trace_pic_ioport_write(s->master, addr, val);
+
if (addr == 0) {
if (val & 0x10) {
pic_init_reset(s);
s->init_state = 1;
s->init4 = val & 1;
s->single_mode = val & 2;
- if (val & 0x08) {
- qemu_log_mask(LOG_UNIMP,
- "i8259: level sensitive irq not supported\n");
- }
+ s->ltim = val & 8;
} else if (val & 0x08) {
if (val & 0x04) {
s->poll = 1;
ret = s->imr;
}
}
- DPRINTF("read: addr=0x%02" HWADDR_PRIx " val=0x%02x\n", addr, ret);
+ trace_pic_ioport_read(s->master, addr, ret);
return ret;
}
-int pic_get_output(DeviceState *d)
+int pic_get_output(PICCommonState *s)
{
- PICCommonState *s = PIC_COMMON(d);
-
return (pic_get_irq(s) >= 0);
}
pc->parent_realize(dev, errp);
}
-void hmp_info_pic(Monitor *mon, const QDict *qdict)
-{
- int i;
- PICCommonState *s;
-
- if (!isa_pic) {
- return;
- }
- for (i = 0; i < 2; i++) {
- s = i == 0 ? PIC_COMMON(isa_pic) : slave_pic;
- monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
- "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
- i, s->irr, s->imr, s->isr, s->priority_add,
- s->irq_base, s->read_reg_select, s->elcr,
- s->special_fully_nested_mode);
- }
-}
-
-void hmp_info_irq(Monitor *mon, const QDict *qdict)
-{
-#ifndef DEBUG_IRQ_COUNT
- monitor_printf(mon, "irq statistic code not compiled.\n");
-#else
- int i;
- int64_t count;
-
- monitor_printf(mon, "IRQ statistics:\n");
- for (i = 0; i < 16; i++) {
- count = irq_count[i];
- if (count > 0) {
- monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
- }
- }
-#endif
-}
-
-qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
+qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
{
qemu_irq *irq_set;
DeviceState *dev;
isadev = i8259_init_chip(TYPE_I8259, bus, true);
dev = DEVICE(isadev);
- qdev_connect_gpio_out(dev, 0, parent_irq);
+ qdev_connect_gpio_out(dev, 0, parent_irq_in);
for (i = 0 ; i < 8; i++) {
irq_set[i] = qdev_get_gpio_in(dev, i);
}
- isa_pic = dev;
+ isa_pic = PIC_COMMON(dev);
isadev = i8259_init_chip(TYPE_I8259, bus, false);
dev = DEVICE(isadev);
PICClass *k = PIC_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->parent_realize = dc->realize;
- dc->realize = pic_realize;
+ device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
dc->reset = pic_reset;
}
projects / mirror_qemu.git / blobdiff