* Copyright (c) 2005-2007 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL
+ * This code is licensed under the GPL
*/
#include "sysbus.h"
#include "primecell.h"
#include "devices.h"
-#include "sysemu.h"
#include "boards.h"
#include "arm-misc.h"
#include "net.h"
+#include "exec-memory.h"
+#include "sysemu.h"
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t memsz;
- uint32_t flash_offset;
+ MemoryRegion flash;
+ bool flash_mapped;
uint32_t cm_osc;
uint32_t cm_ctrl;
uint32_t cm_lock;
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
-static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
+static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
if (offset >= 0x100 && offset < 0x200) {
static void integratorcm_do_remap(integratorcm_state *s, int flash)
{
if (flash) {
- cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
+ if (s->flash_mapped) {
+ sysbus_del_memory(&s->busdev, &s->flash);
+ s->flash_mapped = false;
+ }
} else {
- cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
+ if (!s->flash_mapped) {
+ sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
+ s->flash_mapped = true;
+ }
}
//??? tlb_flush (cpu_single_env, 1);
}
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
- hw_error("Board reset\n");
+ qemu_system_reset_request();
}
- if ((s->cm_init ^ value) & 4) {
+ if ((s->cm_ctrl ^ value) & 4) {
integratorcm_do_remap(s, (value & 4) == 0);
}
- if ((s->cm_init ^ value) & 1) {
- printf("Green LED %s\n", (value & 1) ? "on" : "off");
+ if ((s->cm_ctrl ^ value) & 1) {
+ /* (value & 1) != 0 means the green "MISC LED" is lit.
+ * We don't have any nice place to display LEDs. printf is a bad
+ * idea because Linux uses the LED as a heartbeat and the output
+ * will swamp anything else on the terminal.
+ */
}
- s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
+ /* Note that the RESET bit [3] always reads as zero */
+ s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
}
static void integratorcm_update(integratorcm_state *s)
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
switch (offset >> 2) {
/* Integrator/CM control registers. */
-static CPUReadMemoryFunc * const integratorcm_readfn[] = {
- integratorcm_read,
- integratorcm_read,
- integratorcm_read
-};
-
-static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
- integratorcm_write,
- integratorcm_write,
- integratorcm_write
+static const MemoryRegionOps integratorcm_ops = {
+ .read = integratorcm_read,
+ .write = integratorcm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int integratorcm_init(SysBusDevice *dev)
{
- int iomemtype;
integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
s->cm_osc = 0x01000048;
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
- s->flash_offset = qemu_ram_alloc(0x100000);
+ memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
+ s->flash_mapped = false;
+
+ memory_region_init_io(&s->iomem, &integratorcm_ops, s,
+ "integratorcm", 0x00800000);
+ sysbus_init_mmio(dev, &s->iomem);
- iomemtype = cpu_register_io_memory(integratorcm_readfn,
- integratorcm_writefn, s);
- sysbus_init_mmio(dev, 0x00800000, iomemtype);
integratorcm_do_remap(s, 1);
/* ??? Save/restore. */
return 0;
typedef struct icp_pic_state
{
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
icp_pic_update(s);
}
-static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
+static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
}
static void icp_pic_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
icp_pic_update(s);
}
-static CPUReadMemoryFunc * const icp_pic_readfn[] = {
- icp_pic_read,
- icp_pic_read,
- icp_pic_read
-};
-
-static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
- icp_pic_write,
- icp_pic_write,
- icp_pic_write
+static const MemoryRegionOps icp_pic_ops = {
+ .read = icp_pic_read,
+ .write = icp_pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pic_init(SysBusDevice *dev)
{
icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
- int iomemtype;
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
- iomemtype = cpu_register_io_memory(icp_pic_readfn,
- icp_pic_writefn, s);
- sysbus_init_mmio(dev, 0x00800000, iomemtype);
+ memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
+ sysbus_init_mmio(dev, &s->iomem);
return 0;
}
/* CP control registers. */
-static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
+
+static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
}
static void icp_control_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
switch (offset >> 2) {
case 1: /* CP_FLASHPROG */
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
-static CPUReadMemoryFunc * const icp_control_readfn[] = {
- icp_control_read,
- icp_control_read,
- icp_control_read
-};
-static CPUWriteMemoryFunc * const icp_control_writefn[] = {
- icp_control_write,
- icp_control_write,
- icp_control_write
+static const MemoryRegionOps icp_control_ops = {
+ .read = icp_control_read,
+ .write = icp_control_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void icp_control_init(uint32_t base)
+static void icp_control_init(target_phys_addr_t base)
{
- int iomemtype;
+ MemoryRegion *io;
- iomemtype = cpu_register_io_memory(icp_control_readfn,
- icp_control_writefn, NULL);
- cpu_register_physical_memory(base, 0x00800000, iomemtype);
+ io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
+ memory_region_init_io(io, &icp_control_ops, NULL,
+ "control", 0x00800000);
+ memory_region_add_subregion(get_system_memory(), base, io);
/* ??? Save/restore. */
}
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
- ram_addr_t ram_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- ram_offset = qemu_ram_alloc(ram_size);
+ memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* And again at address 0x80000000 */
- cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
+ memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
- qdev_init(dev);
+ qdev_init_nofail(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(env);
projects / mirror_qemu.git / blobdiff