Revert "Get rid of _t suffix"

[mirror_qemu.git] / hw / iommu.c

diff --git a/hw/iommu.c b/hw/iommu.c
index ee9b78c87b3f421825434ba66d469e1aa1c4fe79..20da7ab969028833694c47e60ed625af95afcd74 100644 (file)
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -21,17 +21,18 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "hw.h"
+
 #include "sun4m.h"
+#include "sysbus.h"
 
 /* debug iommu */
 //#define DEBUG_IOMMU
 
 #ifdef DEBUG_IOMMU
-#define DPRINTF(fmt, args...) \
-do { printf("IOMMU: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
 #endif
 
 #define IOMMU_NREGS         (4*4096/4)
@@ -78,6 +79,19 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 
 #define IOMMU_AFAR          (0x1004 >> 2)
 
+#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
+#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
+#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
+#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
+#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
+#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
+#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
+#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
+#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
+#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
+#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
+#define IOMMU_AER_MASK      0x801f000f
+
 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
@@ -114,6 +128,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 #define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)
 
 typedef struct IOMMUState {
+    SysBusDevice busdev;
     uint32_t regs[IOMMU_NREGS];
     target_phys_addr_t iostart;
     uint32_t version;
@@ -196,6 +211,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
         s->regs[saddr] = val;
         qemu_irq_lower(s->irq);
         break;
+    case IOMMU_AER:
+        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
+        break;
     case IOMMU_AFSR:
         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
         qemu_irq_lower(s->irq);
@@ -220,13 +238,13 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *iommu_mem_read[3] = {
+static CPUReadMemoryFunc * const iommu_mem_read[3] = {
     NULL,
     NULL,
     iommu_mem_readl,
 };
 
-static CPUWriteMemoryFunc *iommu_mem_write[3] = {
+static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
     NULL,
     NULL,
     iommu_mem_writel,
@@ -310,30 +328,17 @@ void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static void iommu_save(QEMUFile *f, void *opaque)
-{
-    IOMMUState *s = opaque;
-    int i;
-
-    for (i = 0; i < IOMMU_NREGS; i++)
-        qemu_put_be32s(f, &s->regs[i]);
-    qemu_put_be64s(f, &s->iostart);
-}
-
-static int iommu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    IOMMUState *s = opaque;
-    int i;
-
-    if (version_id != 2)
-        return -EINVAL;
-
-    for (i = 0; i < IOMMU_NREGS; i++)
-        qemu_get_be32s(f, &s->regs[i]);
-    qemu_get_be64s(f, &s->iostart);
-
-    return 0;
-}
+static const VMStateDescription vmstate_iommu = {
+    .name ="iommu",
+    .version_id = 2,
+    .minimum_version_id = 2,
+    .minimum_version_id_old = 2,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
+        VMSTATE_UINT64(iostart, IOMMUState),
+        VMSTATE_END_OF_LIST()
+    }
+};
 
 static void iommu_reset(void *opaque)
 {
@@ -344,28 +349,39 @@ static void iommu_reset(void *opaque)
     s->regs[IOMMU_CTRL] = s->version;
     s->regs[IOMMU_ARBEN] = IOMMU_MID;
     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
+    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
     s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
-    qemu_irq_lower(s->irq);
 }
 
-void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
+static int iommu_init1(SysBusDevice *dev)
 {
-    IOMMUState *s;
-    int iommu_io_memory;
+    IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
+    int io;
 
-    s = qemu_mallocz(sizeof(IOMMUState));
-    if (!s)
-        return NULL;
+    sysbus_init_irq(dev, &s->irq);
 
-    s->version = version;
-    s->irq = irq;
+    io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
+    sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
 
-    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
-                                             iommu_mem_write, s);
-    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
-
-    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
+    vmstate_register(-1, &vmstate_iommu, s);
     qemu_register_reset(iommu_reset, s);
     iommu_reset(s);
-    return s;
+    return 0;
 }
+
+static SysBusDeviceInfo iommu_info = {
+    .init = iommu_init1,
+    .qdev.name  = "iommu",
+    .qdev.size  = sizeof(IOMMUState),
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
+        DEFINE_PROP_END_OF_LIST(),
+    }
+};
+
+static void iommu_register_devices(void)
+{
+    sysbus_register_withprop(&iommu_info);
+}
+
+device_init(iommu_register_devices)